Ex Parte Youn et al

Patent Trial and Appeal Board

Apr 28, 2016

12705846 (P.T.A.B. Apr. 28, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
121705,846 02/15/2010
74712 7590 05/02/2016
Muir Patent Law, PLLC
P.O. Box 1213
9913 Georgetown Pike, Suite 200
Great Falls, VA 22066
FIRST NAMED INVENTOR
Sunpil Youn
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SAM-256 9446
EXAMINER
LEE, JAE
ART UNIT PAPER NUMBER
2899
NOTIFICATION DATE DELIVERY MODE
05/02/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
pto@muirpatentconsulting.com
eofficeaction@appcoll.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SUNPIL YOUN and KW ANYOUNG OH
Appeal2014-008924
Application 12/705,846
Technology Center 2800
Before TERRY J. OWENS, MICHELLE N. ANKENBRAND, and
CHRISTOPHER C. KENNEDY, Administrative Patent Judges.
OWENS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1, 2, 4, 5, 7-13, 33, 35, 39--41, and 43. We have
jurisdiction under 35 U.S.C. § 6(b).
The Invention
The Appellants claim a multichip package comprising stacked
semiconductor chips. Claim 1 is illustrative:
1. A multichip package comprising:
a substrate;
a plurality of chips mounted to a first surface of the
substrate, the plurality of chips comprising a first chip group of
plural chips and a second chip group of plural chips;
Appeal2014-008924
Application 12/705,846
a ball grid array attached to a second surface of the
substrate providing communication terminals of the package,
the ball grid array comprising a first ball group and a second
ball group;
a first set of electrical connections to transmit at least one
of signals and power, the first set of electrical connections
connecting the first ball group to the first chip group;
a second set of electrical connections to transmit at least
one of signals and power, the second set of electrical
connections connecting the second ball group to the second
chip group,
wherein at least one of the individual balls of the first ball
group has an electrical connection of the first set of electrical
connections to a signal terminal of one chip of the first chip
group and to a signal terminal of a different chip of the first
chip group,
wherein at least one of the individual balls of the second
ball group has an electrical connection of the second set of
electrical connections to a signal terminal of one chip of the
second chip group and to a signal terminal of a different chip of
the second chip group, and
wherein the first ball group is dedicated to the first chip
group and the second ball group is dedicated to the second chip
group.
Iwaya
Yamamoto
Matsui
Fujiwara
The References
US 2002/0056911 Al
US 2009/0218670 Al
US 2009/0219745 Al
US 2009/0096111 Al
The Rejections
May 16, 2002
Sep.3,2009
Sep.3,2009
Apr. 6, 2009
The claims stand rejected as follows: claims 1, 2, 4, 7, 9-13, 33,
and 35 under 35 U.S.C. § 102(e) over Fujiwara, claim 5 under
35 U.S.C. § 103 over Fujiwara in view oflwaya, claim 8 under
35 U.S.C. § 103 over Fujiwara in view of Yamamoto, claims 39--41 under
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Appeal2014-008924
Application 12/705,846
35 U.S.C. § 103 over Fujiwara, and claim 43 under 35 U.S.C. § 103 over
Fujiwara in view of Matsui.
OPINION
We reverse the rejections. We need address only the sole independent
claim, i.e., claim 1. 1 That claim requires a first ball group dedicated to a first
chip group and a second ball group dedicated to a second chip group.
"Anticipation requires that every limitation of the claim in issue be
disclosed, either expressly or under principles of inherency, in a single prior
art reference." Corning Glass Works v. Sumitomo Elec. U.S.A., Inc., 868
F.2d 1251, 1255-56 (Fed. Cir. 1989).
Fujiwara discloses a stacked-chip semiconductor device comprising a
first set of semiconductor chips ( 6, 50) wired to a bump electrode
(unnumbered bump electrode next to bump electrode 5 on the left side of
Figure 6), and a second set of semiconductor chips ( 10, 60) wired to a
different bump electrode (unnumbered bump electrode next to bump
electrode 5 on the right side of Figure 6) (i-fi-f 31, 55-56; Figs. 6, 7).
The Examiner asserts that the Appellants' claim term "dedicated"
"can be broadly and reasonably construed as simply an entity or entities that
has some form of exclusive association with another element or set of
elements" (Ans. 12), and argues that Fujiwara's first set of semiconductor
chips (6, 50) is connected only to a bump electrode on the left side of the
device (1) in Figure 6 and, therefore, is dedicated to the bump electrodes on
1 In the rejections under 35 U.S.C. § 103 the Examiner does not set forth any
obviousness rationale regarding the requirements of the independent claim
(Ans. 7-10).
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Appeal2014-008924
Application 12/705,846
that side of the device ( 1 ), whereas the second set of semiconductor
chips (10, 60) is connected only to a bump electrode on the right side of the
device (1) and, therefore, is dedicated to the bump electrodes on that side of
the device (1) (Ans. 11-12).
"' [D]uring examination proceedings, claims are given their broadest
reasonable interpretation consistent with the specification.'" In re
Translogic Tech. Inc., 504 F.3d 1249, 1256 (Fed. Cir. 2007) (quoting In re
Hyatt, 211F.3d1367, 1372 (Fed. Cir. 2000)). The Appellants' Specification
indicates that the broadest reasonable interpretation of the claim term
"dedicated" consistent with the Specification requires that each package
terminal of a package terminal group (SG 1 or SG2) is connected exclusively
to the semiconductor chips of one chip group (CG 1 or CG2) without being
connected to the semiconductor chips of another chip group (Spec. i-fi-1 45-
46; Figs. lB, 5A).
Fujiwara's Figure 6 shows two bump electrodes (one numbered 5, the
other unnumbered) on each of the left and right sides of the semiconductor
device ( 1 ), but the Examiner has not established that those pairs of bump
electrodes are separate groups such that the outer bump electrodes ( 5),
whose connections are not illustrated, cannot be connected to the same
semiconductor chip set ( 6/50 or 10/60) as the bump electrodes on the other
side of the semiconductor device ( 1 ), or that the semiconductor device ( 1)
includes only the four illustrated bump electrodes and excludes one or more
other bump electrodes which, regardless of their location, can be connected
to the semiconductor chips in either set (6/50 or 10/60).
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Appeal2014-008924
Application 12/705,846
Thus, the Examiner has not established a prima facie case of
anticipation or obviousness of the Appellants' claimed multi chip package.
DECISION/ORDER
The rejections of claims 1, 2, 4, 7, 9-13, 33, and 35 under
35 U.S.C. § 102(e) over Fujiwara, and the rejections under 35 U.S.C. § 103
of claim 5 over Fujiwara in view of Iwaya, claim 8 over Fujiwara in view of
Yamamoto, claims 39--41 over Fujiwara, and claim 43 over Fujiwara in view
of Matsui are reversed.
It is ordered that the Examiner's decision is reversed.
REVERSED
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