Ex Parte Yan et al

Patent Trial and Appeal Board

Aug 10, 2017

13404981 (P.T.A.B. Aug. 10, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/404,981 02/24/2012 Shouli Yan 5797-06100 4827
35690 7590 08/14/2017
MEYERTONS, HOOD, KIVLIN, KOWERT & GOETZEL, P.C.
P.O. BOX 398
AUSTIN, TX 78767-0398
EXAMINER
TRAN, NGUYEN
ART UNIT PAPER NUMBER
2838
NOTIFICATION DATE DELIVERY MODE
08/14/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patent_docketing@intprop.com
ptomhkkg @ gmail .com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHOULI YAN and ALAN WESTWICK1
Appeal 2015-006815
Application 13/404,981
Technology Center 2800
Before CHUNG K. PAK, JAMES C. HOUSEL, and
DEBRA L. DENNETT, Administrative Patent Judges.
PAK, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on an appeal under 35 U.S.C. § 134(a) from the
Examiner’s decision2 rejecting claims 1-21, which are all of the claims
pending in the above-identified application. We have jurisdiction under 35
U.S.C. § 6(b).
We REVERSE.
1 Appellant identifies the real party in interest as “Silicon Laboratories, Inc.”
Appeal Brief filed January 5, 2015 (“App. Br.”) 2.
2 Final Action entered August 1, 2014 (“Final Act.”) 1-11; and the
Examiner’s Answer entered May 14, 2015 (“Ans.”) 2—4.
Appeal 2015-006815
Application 13/404,981
STATEMENT OF THE CASE
The subject matter of the claims on appeal relates to “electronic
circuits, and more particularly, to a voltage regulators] [with a specific
adjustable feedback system].” Spec. 11 and claims 1, 9, and 14. Figure 2,
which is illustrative of such voltage regulator, is reproduced below:
Figure 2 depicts voltage regulator 20 having, inter alia, amplifier A1
receiving a reference voltage Vref on its non-inverting input and a feedback
signal on its inverting input, transistors N1 and N2 directly coupled to the
output of amplifier Al, and a resistor network comprising variable resistors
Rl, R2, and R3. Spec. ]ff[ 18-22. Resistor R3 is provided “between the
inverting input of amplifier Al and each of resistors Rl and R2.” Spec. 1
22. “Resistor Rl... is coupled between the source terminal of transistor N1
and resistor R3. Resistor R2 is coupled between the source terminal of
transistor N2 and resistor R3.” Spec. 122. “The output node of voltage
regulator 20 ... is taken from the source node of transistor N2.” Spec. 123.
“During operation of voltage regulator 20, changes to the load current
caused by changes in a demand from a load may in turn cause at least an
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Application 13/404,981
initial change to the output voltage, Vout. As a result of a change of the
output voltage, the current through at least transistor N2 and resistors R2 and
R3 may change.” Spec. 125.
Details of the appealed subject matter are recited in representative
claims 1, 9, and 14, the broadest claims on appeal, which are reproduced
below from the Claims Appendix of the Appeal Brief (with disputed
limitations in italicized form):
1. A circuit comprising:
an amplifier having a first input configured to receive
a reference voltage and a second input configured to receive
a feedback signal;
first and second transistors each having respective
control terminals coupled directly to an output of the
amplifier, and
a resistor network coupled to the second input of the
amplifier and further coupled to the first and second
transistors, wherein the resistor network is configured to
produce the feedback signal responsive to currents through
the first and second transistors;
wherein the resistor network includes:
a first variable resistor that is adjustable to set
a first contribution to the feedback signal by a source
voltage of the first transistor; and
a second variable resistor that is adjustable to
set a second contribution to the feedback signal by an
output voltage of the circuit;
wherein the first and second variable resistors are
adjustable to provide a continuum of operating points
between a first operating point in which a resistance of the
first variable resistor is effectively infinite and a second
operating point in which a resistance of the second variable
resistor is effectively infinite.
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Application 13/404,981
9. A method comprising:
generating, using an amplifier, an output signal based
on a voltage reference signal received at a first amplifier
input and a feedback signal received at a second amplifier
input;
producing the feedback signal based on currents
flowing through first and second transistors, respectively,
based on the output signal, wherein each of the first and
second transistors include respective control terminals
coupled directly to an output of the amplifier, wherein
producing the feedback signal comprises:
a first variable resistor providing a first contribution to
the feedback signal based on a source voltage of the first
transistor;
a second variable resistor providing a second
contribution to the feedback signal based on an output
voltage of a voltage regulator circuit that includes the
amplifier and the first and second transistors;
wherein the first and second variable resistors are
adjusted to one of a continuum of operating points between a
first operating point in which a resistance of the first variable
resistor is effectively infinite and a second operating point in
which a resistance of the second variable resistor is
effectively infinite.
14. An integrated circuit comprising:
one more load circuits; and
a voltage regulator coupled to generate and provide a
supply voltage to the one or more load circuits, wherein
generating the supply voltage includes:
an amplifier generating an amplifier output voltage
based on a difference between a reference voltage and a
feedback signal;
providing the amplifier output voltage directly to
respective control terminals of first and second transistors',
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Application 13/404,981
generating the feedback signal, wherein a voltage of the
feedback signal is based on currents flowing through the first
and second transistors and through resistors of a resistor
network; and
generating the supply voltage based on current flowing
through the second transistor and a correspondingly coupled
portion of the resistor network;
wherein the resistor network includes:
a first variable resistor to set a first contribution
to the feedback signal by a source voltage of the first
transistor; and
a second variable resistor to set a second
contribution to the feedback signal by an output voltage
of the voltage regulator;
wherein the first and second variable resistors are
adjustable to provide a continuum of operating points between
a first operating point in which a resistance of the first
variable resistor is effectively infinite and a second operating
point in which a resistance of the second variable resistor is
effectively infinite.
App. Br. 23-26, Claims Appendix.
The Examiner maintains, and Appellants seeks review of the
following grounds of rejection:
1) Claims 1^1, 9-13, 14-18, and 21 under 35 U.S.C. § 103(a) as
unpatentable over the combined disclosures of van Ettinger (US 7,656,139
B2 issued Feb. 2, 2010), Geynet (US 8,080,984 B1 issued Dec. 20, 2011),
and Jurasek (US 2011/0102057 A1 published May 5, 2011);
2) Claims 5, 6, and 19 under 35 U.S.C. § 103(a) as unpatentable
over the combined disclosures of van Ettinger, Geynet, Jurasek, and Isobe
(US 2007/0247133 A1 published Oct. 25, 2007);
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3) Claims 7 and 20 under 35 U.S.C. § 103(a) as unpatentable over
the combined disclosures of van Ettinger, Geynet, Jurasek, and Okuyama
(US 7,723,968 B2 issued May 25, 2010); and
4) Claim 8 under 35 U.S.C. § 103(a) as unpatentable over the
combined disclosures of van Ettinger, Geynet, Jurasek, and Kleveland (US
2009/0033298 A1 published Feb. 5, 2009). Final Act. 2-11; Ans. 2-4; App.
Br. 5-21; Reply Brief filed July 14, 2015 (“Reply Br.”) 2-5.
DISCUSSION
Upon consideration of the evidence and arguments advanced by the
Examiner and Appellants, we concur with Appellants that the Examiner has
not demonstrated a prima facie case of obviousness regarding the subject
matter recited in claims 1-21 within the meaning of 35 U.S.C. § 103(a) for
the reasons set forth in the Appeal Brief and Reply Brief. We add the
following for emphasis.
Here, the Examiner’s § 103(a) rejections are all premised upon the
collective teachings of van Ettinger, Geynet, and Jurasek suggesting the
subject matter recited in independent claims 1, 9, and 14, the broadest claims
on appeal, within the meaning of 35 U.S.C. § 103(a). However, as pointed
out by Appellants, the Examiner has not carried the burden of showing that
the collective teachings of van Ettinger, Geynet, and Jurasek would have led
one of ordinary skill in the art to modify the low-dropout voltage (LDO)
regulator taught by van Ettinger in the manner proposed by the Examiner to
arrive at the claimed subject matter. App. Br. 5-21; In re Oetiker, 977 F.2d
1443, 1445 (Fed. Cir. 1992) (“[T]he examiner bears the initial burden, on
review of the prior art or on any other ground, of presenting a prima facie
case of unpatentability.”) On this record, the Examiner, for example, has not
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shown that one of ordinary skill in the art would have been led to eliminate
boost zero compensating resistor Rbz from the low-dropout voltage (LDO)
regulator taught by van Ettinger so as to directly couple its transistor Ml to
the output of its amplifier 213 as required by the claims on appeal. App. Br.
5-18. As correctly explained by Appellants, van Ettinger’s invention lies in
incorporating boost zero compensating resistor Rbz between transistor Ml
and the output of amplifier 213 to overcome “a very serious [stability]
problem” associated with a conventional LDO regulator. App. Br. 5-15;
van Ettinger, col. 1,1. 57-col. 2,1. 44, col. 4,11. 29^43, and col. 5,11. 55—59.
Although the Examiner relies upon Geynet to show direct coupling between
two transistors and the output of an amplifier in the context of Geynet’s
specific voltage regulator configuration that substantially prevents or
interrupts reverse current flow into a voltage regulator from an output
thereof, the Examiner has not shown that such arrangement is applicable to
transistor Ml of the specific low-dropout voltage (LDO) regulator
configuration taught by van Ettinger. Final Act. 3-7; see also Geynet, col.
1,11. 15-20, col. 5,11. 25-41, and Fig. 2. To combine the teachings of van
Ettinger and Geynet in the manner proposed by the Examiner would destroy
the invention on which van Ettinger is based, namely, the use of boost zero
compensating resistor Rbz. Ex parte Hartmann, 186 USPQ 366, 367 (Bd.
App. 1974 )(“Reynolds cannot properly be combined with Graham et al.
relative to the employment of continuous monofilaments since to do so
would destroy that on which the invention of Graham et al. is based, namely,
the use of very short fibers.”)
Accordingly, on this record, we are constrained to reverse the
Examiner’s decision rejecting claims 1-21 based on the proposed
combination of the applied prior art under 35 U.S.C. § 103(a).
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DECISION
Upon consideration of the record, and for the reasons given, it is
ORDERED that the decision of the Examiner to reject claims 1-21
under 35 U.S.C. § 103(a) is REVERSED.
REVERSED
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