Ex Parte Warren

Patent Trial and Appeal Board

Apr 12, 2016

12610208 (P.T.A.B. Apr. 12, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/610,208 10/30/2009 David A. Warren
56436 7590 04/14/2016
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
82259372 9949
EXAMINER
PETRANEK, JACOB ANDREW
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
04/14/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
hpe.ip.mail@hpe.com
mkraft@hpe.com
chris.mania@hpe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte DAVID A. WARREN
Appeal2014-005133
Application 12/610,208
Technology Center 2100
Before JOHN A. EV ANS, MONICA S. ULLAGADDI, and
MATTHEW J. McNEILL, Administrative Patent Judges.
McNEILL, Administrative Patent Judge.
DECISION ON APPEAL
Appellant 1 appeals under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1-14, which are all the claims pending in this application.
We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 According to Appellant, the real party in interest is Hewlett-Packard
Development Company, LP. App. Br. 3.
Appeal2014-005133
Application 12/610,208
STATEMENT OF THE CASE
Introduction
Appellant's present application relates to a hardware pipeline with a
plurality of rows that sequentially executes two or more macros on data as
the data traverses the pipeline. Abstract. Claim 1 is illustrative of the
subject matter on appeal and reads as follows:
1. A device comprising:
a hardware pipeline having a plurality of rows including a
first row, a last row, and an intermediate row between the first
row and the last row, each row to store a number of bytes of data
as the data moves through the hardware pipeline on a row-by-
row basis from the first row towards the last row; and,
a mechanism to perform a first macro on the data
beginning at the first row, and a second macro different than the
first macro on the data beginning at the intermediate row where
the first macro has been completely performed when the data has
reached the intermediate row,
wherein the first macro and the second macro each
comprises a plurality of modifications of the data as the data
moves through the hardware pipeline to effect a complete
transformation of the data, wherein the complete transformation
of the first macro is different from the complete transformation
of the second data, and
wherein the first macro comprises a translation of an
external networking address of the data to an internal networking
address, wherein the external networking address is associated
with an external network and the internal networking address is
associated with a private network.
The Examiner's Rejections
Claims 1-3 and 7-14 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over James-Roxby (US 8,127,262 Bl; Feb. 28, 2012), Morrall
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(US 2006/0215649 Al; Sept. 28, 2006), and Official Notice. See Final Act.
2-8.
Claims 1-3 and 7-14 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Tse-Au (US 2008/0123654 Al; May 29, 2008), Morrall,
and Official Notice. See Final Act. 8-14.
Claims 4-6 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over James-Roxby, Morrall, and Hokenek (US 8,074,051 B2; Dec. 6, 2011).
See Final Act. 14-18.
ANALYSIS
Obviousness over James-Roxby and Morrall
Appellant argues the combination of James-Roxby and Morrall fails
to teach or suggest "wherein the first macro comprises a translation of an
external networking address of the data to an internal networking address,
wherein the external networking address is associated with an external
network and the internal networking address is associated with a private
network." See App. Br. 8-12; Reply Br. 4-7. In particular, Appellant
argues James-Rox by teaches a packet processor that converts pipelined
packet data from one format to another, but does not teach translating the
network address of a packet. App. Br. 11-12. Appellant also argues James-
Roxby does not teach a hardware pipeline, instead disclosing a pipeline
packet processor that is specified in a Hardware Description Language
(HDL). Reply Br. 5. Appellant further argues Morrall discloses conversion
of an IP address to a local address, but the conversion does not occur in a
hardware pipeline. App. Br. 10-11.
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We are not persuaded by Appellants that James-Roxby's teaching of a
pipeline packet processor specified in HDL is not a "hardware pipeline."
The Board "determines the scope of claims in patent applications not solely
on the basis of the claim language, but upon giving claims their broadest
reasonable construction 'in light of the specification as it would be
interpreted by one of ordinary skill in the art."' Phillips v. A WH Corp., 415
F.3d 1303, 1316 (Fed. Cir. 2005) (quoting Jn re Am. Acad. of Sci. Tech. Ctr.,
367 F.3d 1359, 1364 (Fed. Cir. 2004). The Specification does not define the
term "hardware pipeline," but indicates that "pipeline 102 is a hardware
pipeline in that it is implemented in hardware, such as various
semiconductor circuits like application specific integrated circuits
(ASIC's)." Spec. 3:22-24. Accordingly, we conclude the broadest
reasonable interpretation of "hardware pipeline" in light of the Specification
includes at least a pipeline processor that is composed of ASICs.
James-Roxby teaches its pipeline packet processor is defined by an
HDL specification. James-Roxby 4:37--45. James-Roxby teaches
"additional design tools may be used to generate a hardware implementation,
for example, on an application specific integrated circuit (ASIC) or a
programmable logic device, from the pipeline packet processor from the
generated specification." James-Roxby 4:46-50. Thus, James-Roxby
teaches a pipeline processor that may be implemented by ASICs based on
the generated HDL specification, which is within the scope of the broadest
reasonable interpretation of a "hardware pipeline."
Appellant has also not persuaded us the Examiner erred in finding the
combination of James-Roxby and Morrall teaches or suggests a hardware
pipeline that performs a first macro "wherein the first macro comprises a
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translation of an external networking address of the data to an internal
networking address." As found by the Examiner, Morrall teaches translating
global IP addresses to private IP addresses through Network Address
Translation (NAT). Ans. 6; Final Act. 4 (citing Morrall i-fi-1 4, 8, 11 ). As
discussed above, James-Roxby teaches a hardware pipeline that performs
various macros on data in the pipeline. Ans. 6; Final Act. 3 (citing James-
Roxby Fig. 3, Fig. 4, 7:1-16). The proposed combination would use James-
Roxby's hardware pipeline to perform Morrall's address translation. We do
not find Appellant's argument persuasive because Appellant argues
deficiencies in the individual references instead of deficiencies in the
proposed combination. See In re Merck & Co., Inc., 800 F.2d 1091, 1097
(Fed. Cir. 1986); In re Keller, 642 F.2d 413, 425 (CCPA 1981).
Appellant further argues an ordinarily skilled artisan would not have
been motivated to combine James-Roxby and Morrall because James-Roxby
teaches encapsulation of a high-level packet with a low-level packet, which
teaches away from NAT and such combination would change the principle
of operation of James-Roxby. See Reply Br. 6-7. We disagree. As found
by the Examiner, James-Roxby teaches a hardware pipeline processor that
may perform various operations, an example being encapsulation of a high-
level packet with a low-level packet. See Ans. 6 (citing J ames-Roxby 1 :21-
23). However, James-Roxby is not limited to this particular example of
manipulating the content of a packet. See James-Roxby 1: 14-23. Morrall
teaches a packet manipulation wherein NAT is used to convert a global IP
address to a private IP address. Ans. 6; Final Act. 4 (citing Morrall i-fi-1 4, 8,
11 ). Appellant does not present sufficient evidence to persuade us that such
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a packet manipulation would not be appropriate for James-Roxby's
hardware pipeline.
Obviousness over Tse-Au and Morrall
Appellant argues the combination of Tse-Au and Morrall fails to teach
or suggest the "translating" limitation allegedly not taught or suggested by
the combination of James-Roxby and Morrall. See App. Br. 15-18.
Appellant argues Morrall teaches address translation, but fails to teach a
hardware pipeline. App. Br. 16-17. Appellant argues Tse-Au teaches a
hardware pipeline, but fails to teach translating a network address of a
packet in a hardware pipeline. App. Br. 17. Appellant's arguments relating
to the combination of Tse-Au and Morrall have not persuaded us of
Examiner error because Appellant's arguments are directed to the references
individually, instead of the combination as a whole. Accordingly, for
similar reasons to those described above with respect to the combination of
James-Rox by and Morrall, Appellant has failed to persuade us the Examiner
erred in rejecting claim 1 as unpatentable over Tse-Au and Morrall.
Claim 11
Claim 11 recites "The device of claim 1, wherein the second macro
comprises a transformation selected from the group consisting of inserting
tunnel headers, deleting tunnel headers, mirroring packets, inserting virtual
local area network (VLAN) tags, deleting VLAN tags, and modifying
VLAN tags." Appellant argues the Examiner erred in rejecting claim 11 as
unpatentable over James-Roxby, Morrall, and Official Notice. See App. Br.
14-15; Reply Br. 7-8. In particular, Appellant argues James-Roxby teaches
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the encapsulation of high-level packets with low-level packets, which would
not require the use of VLAN tags. App. Br. 14-15. However, as noted
above with respect to claim 1, the proposed combination relies on James-
Roxby's hardware pipeline with Morrall's address translation. With regard
to claim 11, the combination further includes Official Notice of
insertion/removal of VLAN tags for routing packets in a network. See Ans.
7. Appellant has not identified any error in the Examiner's rationale for
combining the references in the proposed manner and has not identified any
deficiency in the proposed combination, instead attacking the James-Roxby
reference individually. Accordingly, Appellant's argument has not
persuaded us the Examiner erred in rejecting claim 11.
Claims 4-6
Appellant argues the Examiner erred in rejecting claim 4-6 because
the rejection fails to include Official Notice, which is included in the
rejection of claim 1 from which claims 4-6 depend. See App. Br. 19-20;
Reply Br. 12-13. The Examiner responds that the omission of Official
Notice from the rejection of claims 4-6 is a typographical error and does not
constitute "clear error." Ans. 10-11.
Appellant is correct that the rejection of claims 4-6 should include the
Official Notice that is relied upon in rejecting independent claim 1, from
which these claims depend. However, we find this to be a harmless error
because the Examiner has not relied upon the Official Notice in rejecting
any of the limitations added by dependent claims 4-6. See Final Act. 14-18.
Further, in the rejection of claim 1, the Examiner explains the use of Official
Notice in the combination. See Final Act. 3. Accordingly, Appellant had an
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opportunity to respond to the use of Official Notice with respect to claim 1
and the typographical error which resulted in the omission of Official Notice
from claims 4-6 has not prejudiced Appellant.
CONCLUSIONS
On the record before us and in view of the analysis above, Appellant
has not persuaded us that the Examiner erred in rejecting claim 1 as
unpatentable over James-Roxby, Morrall, and Official Notice. Therefore,
we sustain the rejection of claim 1 under 35 U.S.C. § 103(a) as unpatentable
over James-Roxby, Morrall, and Official Notice. Appellant argues the
patentability of claims 10 and 13 based on the same reasons presented for
claim I. See App. Br. 13-14. We, therefore, sustain the rejection of claims
10 and 13 under 35 U.S.C. § 103(a) as unpatentable over James-Roxby,
Morrall, and Official Notice for the same reasons as set forth above. We
also sustain the rejection of claims 2, 3, 7-9, 12, and 14 under 35 U.S.C.
§ 103(a) as unpatentable over James-Roxby, Morrall, and Official Notice
because these claims were not argued separately. See App. Br. 14-15.
On the record before us and in view of the analysis above, Appellant
has not persuaded us that the Examiner erred in rejecting claim 1 as
unpatentable over Tse-Au, Morrall, and Official Notice. Therefore, we
sustain the rejection of claim 1 under 35 U.S.C. § 103(a) as unpatentable
over Tse-Au, Morrall, and Official Notice. Appellant argues the
patentability of claims 10 and 13 based on the same reasons presented for
claim 1. See App. Br. 18-19. We, therefore, sustain the rejection of claims
10 and 13 under 35 U.S.C. § 103(a) as unpatentable over Tse-Au, Morrall,
and Official Notice for the same reasons as set forth above. We also sustain
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the rejection of claims 2, 3, 7-9, 11, 12, and 14 under 35 U.S.C. § 103(a) as
unpatentable over Tse-Au, Morrall, and Official Notice because these claims
were not argued separately. See App. Br. 18.
On the record before us and in view of the analysis above, Appellant
has not persuaded us that the Examiner erred in rejecting claim 11.
Therefore, we sustain the rejection of claim 11 under 35 U.S.C. § 103(a) as
unpatentable over James-Roxby, Morrall, and Official Notice.
On the record before us and in view of the analysis above, Appellant
has not persuaded us that the Examiner erred in rejecting claims 4-6 as
unpatentable over James-Roxby, Morrall, and Hokenek. Therefore, we
sustain the rejection of claims 4-6 under 35 U.S.C. § 103(a) as unpatentable
over James-Roxby, Morrall, and Hokenek.
DECISION
The decision of the Examiner to reject claims 1-14 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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