Ex Parte Tamura et al

Patent Trial and Appeal BoardAug 30, 2017

13950957 (P.T.A.B. Aug. 30, 2017)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/950,957 07/25/2013 Tomoko TAMURA 0756-10199 1083 31780 7590 09/01/2017 Robinson Intellectual Property Law Office, P.C. 3975 Fair Ridge Drive Suite 20 North Fairfax, VA 22033 EXAMINER NEWTON, VALERIE N ART UNIT PAPER NUMBER 2897 NOTIFICATION DATE DELIVERY MODE 09/01/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ptomail @ riplo .com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte TOMOKO TAMURA, EIJI SUGIYAMA, YOSHITAKA DOZEN, KOJI DAIRIKI, and TAKUYA TSURUME (Applicant: Semiconductor Energy Laboratory Co., Ltd.) Appeal 2015-008141 Application 13/950,957 Technology Center 2800 Before CARLA M. KRIVAK, JASON V. MORGAN, and KARA L. SZPONDOWSKI, Administrative Patent Judges. SZPONDOWSKI, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s Final Rejection of claims 2—6, 8—15, 17—23, and 25—27. Claims 7, 16, and 24 are cancelled. App. Br. 17, 18, 20, Claims App’x. We have jurisdiction under 35 U.S.C. § 6(b). An oral hearing was held on July 25, 2017. We REVERSE. Appeal 2015-008141 Application 13/950,957 STATEMENT OF THE CASE Appellants’ invention is directed to a method for manufacturing a semiconductor device, and in particular to a method for peeling a thin film integrated circuit. Spec. 1. Claim 2, reproduced below with the disputed limitations in italics, is illustrative of the claimed subject matter: 2. A method for manufacturing a semiconductor device, comprising the steps of: forming a first layer over a first substrate; forming a second layer including a transistor over the first layer, wherein the second layer has an opening, and a part of a top surface of the first layer is exposed in the opening of the second layer; after the part of the top surface of the first layer is exposed, partly removing the first layer by etching, wherein an etchant is introduced through the opening of the second layer, and a part of the first layer is left unremoved so that the second layer remains attached to the first substrate by the part of the first layer, attaching a second substrate to the second layer after partly removing the first layer; separating the second layer from the first substrate after attaching the second substrate to the second layer; attaching the second layer to a third substrate after separating the second layer from the first substrate; and removing the second substrate from the second layer. 2 Appeal 2015-008141 Application 13/950,957 REJECTIONS Claims 2, 3, 6, 8, 9, 19, 20, 23, and 25—27 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Yamazaki et al. (US 2001/0015256 Al; published Aug.23, 2001) (“Yamazaki”). Final Act. 2. Claims 4, 5, 10-15, 17, 18, 21, and 22 stand rejected under 35 U.S.C. § 103(a) as being unpatentable the combination of Yamazaki and Shimoda et al. (2003/0022403 Al; published Jan. 30, 2003 (“Shimoda”). Final Act. 4. ANALYSIS Issue: Did the Examiner err in finding Yamazaki teaches or suggests “partly removing the first layer by etching . . . and a part of the first layer is left unremoved so that the second layer remains attached to the first substrate by the part of the first layer,” as recited in independent claim 2 and commensurately recited in independent claims 10 and 19? The Examiner relies primarily on Figure 4E and paragraphs 55—57 of Yamazaki to teach or suggest the disputed limitations. Final Act. 2. The Examiner finds “the recitation [in paragraph 57] that the substrate is bonded to the first substrate by the second layer does not preclude the existence of the peeling layer formed on the substrate enclosed by the resin/polyimide layer.” Advisory Action 2 (mailed Sept. 26, 2014), (citing Yamazaki 145). Further, the Examiner finds Yamazaki’s paragraph 56 states that “the throughput of the removing process of the peeling layer 102 can be improved in Embodiment 1 [,]... . suggests that the removal of the peeling layer in the embodiment 1 as compared to the other embodiment modes is not complete and that there will remain a portion of the peeling layer even 3 Appeal 2015-008141 Application 13/950,957 after the etching process is concluded,” thus teaching the disputed limitation. Ans. 2. Appellants argue “in Yamazaki... the alleged first layer (i.e., peeling layer 102 of resist material) appears to be thoroughly removed by etching so that NO part of the first layer is left unremoved.” App. Br. 9; see also App. Br. 10-13. We agree with Appellants the Examiner has not sufficiently established that Yamazaki teaches, suggests, or otherwise renders obvious the disputed limitation. The Examiner’s findings do not point to any express disclosure in Yamazaki that the peeling layer is only partially removed, rather than completely removed. See Yamazaki | 55 (“thereby remove the peeling layer”); Yamazaki | 57 (“the removing process of the peeling layer”); Yamazaki 145 (“the peeling layer 102 is completely removed”). Accordingly, we are persuaded the Examiner erred in rejecting independent claims 2, 10, and 19, and, therefore, do not sustain those rejections. For the same reasons we do not sustain the Examiner’s rejections of dependent claims 3—6, 8, 9, 11—15, 17, 18, 20-23, and 25—27. DECISION For the above reasons, the Examiner’s rejection of claims 2—6, 8—15, 17—23, and 25—27 is reversed. REVERSED 4