Ex Parte Shreiner

Patent Trial and Appeal Board

Aug 31, 2017

13552090 (P.T.A.B. Aug. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/552,090 07/18/2012 David Robert SHREINER SCS-550-1532 6482
73459 7590 09/05/2017
NIXON & VANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203
EXAMINER
HE, WEIMING
ART UNIT PAPER NUMBER
2612
NOTIFICATION DATE DELIVERY MODE
09/05/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon @ firsttofile. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DAVID ROBERT SHREINER
Appeal 2017-001407
Application 13/5 52,09c1
Technology Center 2600
Before JOHN A. JEFFERY, MARC S. HOFF, and
KRISTEN L. DROESCH, Administrative Patent Judges.
HOFF, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from a Final Rejection of
claims 1—20. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appellant’s invention is a graphics processing unit. A shader
execution unit executes a plurality of shader routines in order to perform a
predetermined sequence of shader operations, including a tessellation
operation that receives as inputs tessellation control data and an input list of
input data for M input vertices, and generates output data for P output
1 The real party in interest is ARM Limited.
Appeal 2017-001407
Application 13/552,090
vertices. For each output vertex, the controller allocates a tessellation shader
routine, and the shader execution unit is configured, each time the
tessellation shader routine is executed for an associated output vertex: (i) to
compute, in dependence on the tessellation control data and the associated
output vertex, tessellation coordinate data; and (ii) to compute from the input
data for the M input vertices, and the tessellation coordinate data generated
in step (i), the output data for the associated output vertex. See Abstract.
Claim 1 is exemplary of the claims on appeal:
1. A graphics processing apparatus comprising:
shader execution circuitry configured to execute a plurality of shader
routines in order to perform a predetermined sequence of shader operations;
rendering circuitry configured to perform at least one rendering
operation on data output by the shader execution circuitry;
control circuitry configured to allocate to the shader execution
circuitry individual shader routines from a set of shader routines, in order to
cause the predetermined sequence of shader operations to be performed;
the predetermined sequence of shader operations including a
tessellation setup operation, the tessellation setup operation receiving as an
input an initial list of initial data for N initial vertices, and generating as
outputs an input list of input data for M input vertices and tessellation
control data;
the predetermined sequence of shader operations further including a
tessellation operation, the tessellation operation receiving as inputs said
tessellation control data and said input list of input data for M input vertices,
and generating at least output data for P output vertices;
the control circuitry is configured to cause the tessellation operation to
be performed by allocating to the shader execution circuitry, for each output
vertex of the P output vertices, a tessellation shader routine from said set of
shader routines;
the shader execution circuitry configured, each time the tessellation
shader routine is executed for an associated output vertex, to:
(iii) compute, in dependence on the tessellation control data and
the associated output vertex, tessellation coordinate data; and to
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Application 13/552,090
(iv) compute from the input data for the M input vertices, and
the tessellation coordinate data, the output data for the associated
output vertex.
The Examiner relies upon the following prior art in rejecting the
claims on appeal:
Moreton US 7,142,206 B1 Nov. 28,2006
Rhoades US 2011/0080404 A1 Apr. 7, 2011
Legakis US 8,599,202 B1 Dec. 3,2013
Claims 1—7, 9, 14—16, and 18—20 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Rhoades, Applicant’s Admitted Prior
Art (AAPA), and Moreton.
Claims 8, 10-13, and 17 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Rhoades, AAPA, Moreton, and Legakis.
Throughout this decision, we refer to the Appeal Brief (“App. Br.,”
filed Jan. 19, 2016), the Reply Brief (“Reply Br.,” filed Nov. 1, 2016), and
the Examiner’s Answer (“Ans.,” mailed Sept. 1, 2016) for their respective
details.
ISSUE
Does the combination of Rhoades, AAPA, and Moreton teach or
suggest shader execution circuitry configured, each time the tessellation
shader routine is executed for an associated output vertex, to compute, in
dependence on the tessellation control data and the associated output vertex,
tessellation coordinate data?
ANALYSIS
Claims 1-7,9,14—16, and 18-20
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Application 13/552,090
Independent claim 1 recites, inter alia, shader execution circuitry
configured, each time the tessellation shader routine is executed for an
associated output vertex, to “(i) compute, in dependent on the tessellation
control data and the associated output vertex, tessellation coordinate data.”
Independent claims 18 and 19 recite effectively identical limitations.
As Appellant discloses, when seeking to render complex shapes in
order to produce a graphics image for display, those complex shapes
typically first need to be converted into meshes of standard rendering
primitives (e.g., triangles). The desired graphics image can then be
generated from the resulting mesh data. The process of converting such
complex shapes into meshes of standard rendering primitives is referred to
as “tessellation.” See Spec. 1.
As illustrated in Appellant’s Figure 1, the prior art graphics
application programming interface (API) includes a tessellation phase
composed of two programmable shader stages along with a fixed-function
tessellator block. Spec. 2.
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10
Figure 1 is a diagram schematically illustrating components used to
perform tessellation in accordance with known modem graphics APIs.
Spec. 10.
Hull shader stage 15 and domain shader stage 25 are implemented by
corresponding shader routines executed by a shader execution unit of the
graphics processing unit (GPU). Spec. 2. The hull shader stage 15 specifies
a list of vertices to be provided as input to the domain shader stage 25. Id.
A domain shader routine is executed by the domain shader stage 25,
the domain shader stage performing operations on each mesh vertex output
by the tessellator 20. The domain shader may potentially transform the
vertex’s data, with the results being written out as the mesh vertex data 30
for use in downstream processing. See Spec. 2.
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Application 13/552,090
Appellant discloses that in the prior art, tessellator 20 becomes a
synchronization point that creates a pipeline dependency within the shader
execution circuitry. This pipeline dependency is removed in the invention,
because tessellation coordinate data is generated on the fly as the tessellation
shader routine executes, with said tessellation coordinate data being
consumed by the tessellation shader routine during claim step (ii) that
generates the output data for the associated output vertex. App. Br. 10-11.
Appellant argues that the Examiner’s combination of Rhoades,
AAPA, and Moreton fails to teach or suggest “shader execution circuitry
configured, each time the tessellation shader routine is executed for an
associated output vertex, to compute, in dependence on the tessellation
control data and the associated output vertex, tessellation coordinate data,”
as claim 1 requires. App. Br. 12. We find Appellant’s argument to be
persuasive.
The Examiner finds that Rhoades discloses a “hull shader operation to
process surface patches (including N vertices) and output tessellation control
data (tessellation [level-of-detail LOD] values) and tessellation data for each
surface patch.” Ans. 3. The Examiner further notes that Appellant admits
that “this Hull shader operation also being referred to herein as a tessellation
setup operation,” that it operates in “the conventional manner;” the
Examiner concludes from this admission that it is reasonable to interpret the
claimed hull shader as working in the same way as the hull shader program
of Rhodes, to wit, performing the tessellation setup operation to process the
incoming patches with initial N vertices and output tessellation control data.
Id. The Examiner finds that Rhoades teaches a domain shader, and that
Moreton discloses a “graphics 50 pipeline portion 100 compris[ing]
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tessellation setup 101 and tessellator 102.” Ans. 4, citing Moreton col 5:48—
65.
Nevertheless, the Examiner’s rejection does not explain where
Rhoades or Moreton teaches or suggests shader execution circuitry that
computes, in dependence on the tessellation control data and the associated
output vertex, tessellation coordinate data, as required by the claims. We
agree with Appellant that Rhoades is silent as to how the parametric position
for each vertex, i.e., the “tessellation coordinate data,” is generated from the
tessellation control data produced by the Hull shader. See App. Br. 14.
Rhoades discloses that “[a] domain shader program may compute a final
position and attributes of each tessellated vertex based on the patch primitive
control points, a parametric (u,v) position for each vertex, displacement
maps, and the like, and is executed once for each output vertex.” Rhoades
179. Rhoades thus teaches Appellant’s claim limitation (ii), the domain
shader that “computes from the input data for the M input vertices, and the
tessellation coordinate data, output data for the associated output.”
However, Rhoades fails to teach Appellant’s limitation (i), “computing, in
dependence on the tessellation control data and the associated output vertex,
tessellation coordinate data.”
We agree with Appellant that because the invention in Rhoades is not
concerned with generating tessellation coordinate data, the person having
ordinary skill in the art would assume that said tessellation coordinate data
as used in Rhoades would be generated in the standard manner using a fixed
function tessellator, like tessellator 20 in Appellant’s Prior Art Figure 1.
App. Br. 14.
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The Examiner’s Response to Arguments section explicitly
acknowledges Appellant’s argument that Rhoades does not teach the
claimed computation of tessellation coordinate data. Ans. 6—7. The
Examiner then refers to Rhoades generating “tessellation data,” including
level-of-detail values that the Examiner finds refer to “tessellation control
data.” Ans. 7. The Examiner’s response does not in any way rebut
Appellant’s argument that the combination of references fails to teach
computation of tessellation coordinate data.
We find that the combination of Rhoades, AAPA, and Moreton fails
to teach all the limitations of independent claims 1,18, and 19. Thus, we do
not sustain the Examiner’s § 103(a) rejection of claims 1,18, and 19, as well
as the rejection of dependent claims 2—7, 9, 14—16, and 20, not separately
argued.
Claims 8,10-13, and 17
Each of these claims depends, ultimately, from independent claim 1.
As explained supra, we do not sustain the rejection of claim 1 over Rhoades,
AAPA, and Moreton. We have reviewed Legakis, and we find that it does
not remedy the deficiencies in the Examiner’s combination. Therefore, we
do not sustain the Examiner’s rejection of claims 8, 10-13, and 17, for the
same reasons expressed with respect to parent claim 1, supra.
CONCLUSION
The combination of Rhoades, AAPA, and Moreton does not teach or
suggest shader execution circuitry configured, each time the tessellation
shader routine is executed for an associated output vertex, to compute, in
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dependence on the tessellation control data and the associated output vertex,
tessellation coordinate data.
ORDER
The Examiner’s decision to reject claims 1—20 under 35 U.S.C.
§ 103(a) is reversed.
REVERSED
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