Ex Parte Ryoo

Patent Trial and Appeal Board

Apr 1, 2016

13237804 (P.T.A.B. Apr. 1, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/237,804 09/20/2011 Jae Kwan Ryoo
20792 7590 04/01/2016
MYERS BIGEL & SIBLEY, PA
PO BOX 37428
RALEIGH, NC 27627
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
5649-3371 2027
EXAMINER
YEN, PAUL TIJEI-FU
ART UNIT PAPER NUMBER
2116
MAILDATE DELIVERY MODE
04/01/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JAE KWAN RY00 1
Appeal2014-003514
Application 13/237,804
Technology Center 2100
Before ALLEN R. MacDONALD, KEVIN C. TROCK, and
AMBER L. HAGY, Administrative Patent Judges.
HAGY, Administrative Patent Judge.
DECISION ON APPEAL
1 Appellant identifies Samsung Electronics Co., Ltd., as the real party in
interest. (App. Br. 1.)
Appeal2014-003514
Application 13/237,804
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1-12, 14, and 15. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Introduction
According to Appellant, "[t]he inventive subject matter relates to
power management for processor integrated circuits and, more particularly,
to apparatus and methods for controlling a power supply voltage provided to
a processor." (Spec. i-f 2.)
Exemplary Claim
Claim 1, reproduced below, is exemplary of the claimed subject
matter:
1. A method of operating an integrated circuit, the method
compnsmg:
determining a difference between a reference level and a
level of a power supply voltage at a power input of a data
processor circuit of the integrated circuit, wherein the power
input of the data processor circuit is connected to a power
management integrated circuit via a power pin;
generating a digital code responsive to the determined
difference; and
transmitting the digital code to the power management
integrated circuit via at least one data pin.
2
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Application 13/237,804
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Kim et al. ("Kim")
Reddy et al. ("Reddy")
Muresan et al. ("Muresan")
Voo
us 6,115,822
US 2008/0282102 Al
US 7,716,502 B2
US 7,872,372 Bl
REJECTIONS 2
Sept. 5, 2000
Nov. 13, 2008
May 11, 2010
Jan. 18, 2011
Claims 1-5, 7, 9, 11, 14, and 15 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Muresan and Reddy. (Final Act. 3-13.)
Claims 6 and 10 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Muresan, Reddy, and Voo. (Final Act. 13-14.)
Claims 8 and 12 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Muresan, Reddy, and Kim. (Final Act. 14--15.)
ISSUES
( 1) Whether the Examiner erred in finding the combination of
Muresan and Reddy teaches or suggests "determining a difference between a
reference level and a level of a power supply voltage at a power input of a
data processor circuit of the integrated circuit," as recited in independent
claim 1.
(2) Whether the Examiner erred in combining the teachings of
Muresan and Reddy.
2 Although the Examiner also rejected claim 13 in the Final Action,
Appellant canceled claim 13 in an amendment after final dated September
10, 2013. The Examiner entered the amendment in an Advisory Action
dated September 18, 2013.
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Application 13/237,804
ANALYSIS
We have reviewed the Examiner's rejections of the claims in light of
Appellant's arguments the Examiner has erred. We disagree with
Appellant's conclusions and we adopt as our own: (1) the findings and
reasons set forth by the Examiner in the action from which this appeal is
taken (Final Act. 2-15) and (2) the reasons set forth by the Examiner in the
Examiner's Answer in response to Appellant's Appeal Brief. (Ans. 2-7.)
We concur with the conclusions reached by the Examiner, and we highlight
the following for emphasis. 3
The Examiner cites Muresan as teaching or suggesting "determining a
difference between a reference level and a level of a power supply voltage"
as recited in independent claim 1, finding Muresan discloses "power-smart
control block compares isense signal to a reference current value Iref .... "
(Final Act. 4 (citing Muresan, col. 15, 11. 6-15).) Citing Ohm's Law, which
the Examiner notes "states the proportional relationship between current and
voltage (V=IR)," the Examiner further finds:
[W]hile Muresan discloses comparisons between current values
rather than voltage, it is well-known in the art that voltage and
current are proportionally related. It would have been obvious
to one of ordinary skill in the art to replace the current values in
Muresan with voltage values to obtain proportionally equal
results of determined differences.
(Final Act. 4; Ans. 3.)
Appellant argues "the proposed application of Ohm's Law is a
misapplication in the context of Muresan" (Reply Br. 2.), asserting "[t]here
3 Only those arguments made by Appellant have been considered in this
decision. Arguments Appellant did not make in the briefs have not been
considered and are deemed to be waived. See 37 C.F.R. § 41.37(c)(l)(iv).
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Appeal2014-003514
Application 13/237,804
is no basis for modifying [Muresan's] operation to use power supply
voltage, as there is no basis for concluding that power supply voltage
provides the same information about processor core operations as current."
(App. Br. 6 (emphases added).) Appellant, however, provides no factual
support for this argument. As our reviewing court has noted, unsupported
attorney argument is entitled to little probative value. In re Geisler, 116
F.3d 1465, 1470 (Fed. Cir. 1997); In re De Blauwe, 736 F.2d 699, 705 (Fed.
Cir. 1984). Moreover, contrary to Appellant's unsupported contentions, it
was known in the art that "power analysis attacks," as addressed in Muresan,
could be conducted not only by sampling current but also by sampling
voltage. Indeed, as the Examiner finds, Muresan recognizes that "power
consumption is monitored by using current sensors or by measuring the
voltage drop across a small resistor placed in series with the power supply
path of the cryptosystem." (Ans. 3 (citing (Muresan, col. 2, 11. 13-15).) See
also S. Almanei, Protecting Smart Cards from Power Analysis Attacks,
Dept. of Electrical & Comp. Engineering 1, 1--4 (2002), http://www.cs.ucsb.
edu/~koc/cren/project/pp/almanei.pdf ("To measure the circuit's power
consumption, a small (e.g., 50 ohm) resistor is inserted in series with the
power or ground input. The voltage difference across the resistor divided by
the resistance yields the current.").
Appellant further argues:
Fig. 1 of Muresan shows an integrated circuit (IC) that
receives power at first and second power terminals VDD, GND.
In a typical electronics application using ICs, the voltage VDD
is regulated, e.g., a power supply producing the voltage acts to
maintain the voltage VDD at a relatively constant level over a
range of currents drawn from the power supply. The system
follows Ohm's Law in the sense that the regulation changes the
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Application 13/237,804
impedance presented by the power supply changes as current
drawn by the IC changes in order for the voltage VDD to be
maintained. Contrary to the assertion of the Answer that "there
does not appear to be a change in the load" (Answer, p. 3), the
load does change, i.e., it draws differing amounts of current.
However, the voltage VDD does not vary the same way
the current varies because of the action of the regulator.
Therefore, the voltage VDD does not provide the same
information as the current for the purposes described in
Muresan, which is addressed to thwarting security attacks
trying to detect processes within the IC by detecting current
variations that are correlated with such processes.
(Reply Br. 2 (emphasis added).)
We are not persuaded by Appellant's arguments, which ignore the
creativity of an ordinarily skilled artisan. The artisan is not compelled to
blindly follow the teaching of one prior art reference over the other without
the exercise of independent judgment. See Lear Siegler, Inc. v. Aeroquip
Corp., 733 F.2d 881, 889 (Fed. Cir. 1984). Rather, as the Supreme Court
has explained, the skilled artisan would "be able to fit the teachings of
multiple patents together like pieces of a puzzle" because the skilled artisan
is "a person of ordinary creativity, not an automaton." KSR Int 'l Co. v.
Teleflex Inc., 550 U.S. 398, 420-21 (2007). In addition, even if measuring
differences in voltage as opposed to differences in current does not provide
"the same information ... for the purposes described in Muresan" (Reply
Br. 2), those purposes are not reflected in Appellant's claim 1. Rather, as
the Examiner finds, and we agree, "Muresan suggests the current being
sensed could just as well be replaced with voltage and perform the same
function" sufficient for purposes of the invention recited in claim 1. (Ans.
3.)
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Appellant also argues the Examiner's findings regarding the combined
teachings of Muresan and Reddy are in error because "Muresan and Reddy
are not properly combinable." (App. Br. 6.) In particular, although
Appellant acknowledges Muresan suggests the processor core may be
separate from the power management system, Appellant argues Muresan
teaches that they be separated on different silicon layers, instead of being
connected "via a power pin," as recited in claim 1. (App. Br. 6 (citing
Muresan, col. 9, 11. 16-22).) Appellant further argues "Muresan actually
teaches away from coupling of the current flattening device [of Muresan] to
the processor core via a power pin, as this would undermine the purpose of
the circuitry described in Muresan." (Id. (emphasis added).)
We are not persuaded by Appellant's arguments. As the Examiner
finds, and we agree, "Muresan does not teach away from the use of pins,
since the sensed current and reference current are connected to the voltage
regulator through pins as shown in Figure 16 .... " (Ans. 4--5.) Moreover,
the portion of Muresan cited by Appellant does not disparage or discredit
use of pins; rather, it describes implementing on "separate silicon layers" as
an "example": "The system can, for example, be implemented as an
integrated system-on-chip. Alternatively, the current flattening device can
be implemented separate from the core,for example on separate silicon
layers, with the layers secured together using known techniques to create an
integrated tamper resistant system." (Muresan, col. 9, 11. 19--21 (emphasis
added).)
Appellant also challenges the Examiner's combination of Muresan
and Reddy on the grounds that the manner in which Reddy discloses
providing a voltage value to the power management unit is not compatible
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with generating a digital code responsive to a dij)erence between the
reference level and a level of a power supply voltage, because Reddy
discloses choosing an optimal voltage value based on a frequency value.
(App. Br. 7; Reply Br. 3.) Appellant's argument is unpersuasive as failing to
respond to the Examiner's rejection. The Examiner cited Muresan, not
Reddy, as teaching "determining a difference between a reference level and
a level of a power supply," and "generating a digital code responsive to the
determined difference." (Final Act. 4.) Also as explained supra, we concur
with the Examiner's findings regarding the teachings of Muresan.
Appellant also argues "the Final Action and the Answer provide no
explanation has to how the architecture of Reddy would work with the
architecture described in Muresan." (Reply Br. 3.) Appellant's argument is
unpersuasive, as it relies on the premise that the references cannot be
physically combined. "[I]t is not necessary that the inventions of the
references be physically combinable to render obvious the invention under
review." In re Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983) (citing
Orthopedic Equip. Co., Inc. v. United States, 702 F.2d 1005, 1013 (Fed. Cir.
1983); In re Andersen, 391F.2d953, 958 (CCPA 1968)); see also In re
Nievelt, 482 F.2d 965, 968 (CCPA 1973) ("Combining the teachings of
references does not involve an ability to combine their specific structures.").
"The test for obviousness is not whether the features of a secondary
reference may be bodily incorporated into the structure of the primary
reference . . . . Rather, the test is what the combined teachings of the
references would have suggested to those of ordinary skill in the art." In re
Keller, 642 F.2d 413, 425 (CCPA 1981) (citations omitted).
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For the foregoing reasons, we are unpersuaded of error in the
Examiner's 35 U.S.C. § 103(a) rejection of claim 1. We, therefore, sustain
that rejection, along with the rejection of dependent claims 2--4, which
Appellant does not argue separately from claim 1. (App. Br. 9.) 37 C.F.R.
§ 41.37(c)(l)(iv).
Appellant also does not present separate substantive arguments for
independent claims 5 and 9. Instead, Appellant refers summarily to, and
incorporates, Appellant's arguments made in connection to claim 1. (App.
Br. 7-9.) Therefore, for the reasons stated above regarding claim 1, we are
not persuaded of error in the Examiner's 35 U.S.C. § 103(a) rejection of
claims 5 and 9. We, therefore, sustain that rejection, along with the rejection
of dependent claims 6-8, 10-12, 14, and 15, which Appellant does not argue
separately from claims 5 and 9. (App. Br. 9.) 37 C.F.R. § 41.37(c)(l)(iv).
DECISION
For the above reasons, the Examiner's rejection of claims 1-12, 14,
and 15 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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