Ex Parte Quddus

Patent Trial and Appeal Board

Oct 2, 2017

13706911 (P.T.A.B. Oct. 2, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/706,911 12/06/2012 Wasim Quddus SIL.0204US (D-12-610-07) 1087
21906 7590 10/04/2017
TROP, PRUNER & HU, P.C.
1616 S. VOSS ROAD, SUITE 750
HOUSTON, TX 77057-2631
EXAMINER
ZAMAN, FAISAL M
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
10/04/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
tphpto@tphm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte WASIM QUDDUS1
Appeal 2017-004183
Application 13/706,911
Technology Center 2100
Before CARLA M. KRIVAK, KARA L. SZPONDOWSKI, and
DAVID J. CUTITTAII, Administrative Patent Judges.
CUTITTA, Administrative Patent Judge.
DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1—6, 8—11, 13, 14, and 16—20, all pending claims of
the application.2 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 According to Appellant, the real party in interest is Silicon Laboratories
Inc. Appeal Br. 3.
2 Claims 7, 12, and 15 are cancelled. Appeal Br. 17—18.
Appeal 2017-004183
Application 13/706,911
STATEMENT OF THE CASE
According to Appellant, the application relates to permitting “a
processing core to efficiently access program instructions and program data
in a manner, which may be advantageous for purposes of minimizing or
preventing arbitration cycles due to a processing core switching between
non-volatile and volatile memory accesses.” Spec. 1 ll.* * 3 Claims 1, 8, and
13 are independent. Claims 1,8, and 17 are illustrative and are reproduced
below with disputed limitations italicized:
1. A method comprising:
receiving a request from a master device for a bus
transfer targeting a slave device of a plurality of slave devices
associated with a slave port of bus switching fabric, the slave
port being shared among the plurality of slave devices;
in response to the request, multiplexing use of the slave
port among the plurality of slave devices; and
using a register to program register data to control
whether a first slave device of the plurality of slave devices
shares the slave port with a second slave device of the plurality
of slave devices.
8. An apparatus comprising:
a bus matrix circuit comprising a slave port and a master
port, the slave port being shared among a plurality of slave
devices, the plurality of slave devices comprising a first slave
device and a second slave device;
a multiplexer adapted to respond to a request initiated by
a master coupled to the master port for a bus transfer to access a
3 This Decision refers to: (1) Appellant’s Specification filed December 6,
2012 (Spec.); (2) the Final Office Action (Final Act.) mailed May 19, 2016;
(3) the Appeal Brief (Appeal Br.) filed October 18, 2016; (4) the Examiner’s
Answer (Ans.) mailed November 17, 2016 and (5) the Reply Brief (Reply
Br.) filed January 17, 2017.
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Application 13/706,911
first slave device of the plurality of slave devices to selectively
couple the first slave device to the slave port; and
a register coupled to the bus matrix circuit to store data,
the register adapted to control whether the first slave device
shares the slave port with the second slave device.
17. The apparatus of claim 13, wherein the bus matrix
circuit is adapted to cause the processing core to perceive the
non-volatile and volatile memory devices as collectively being a
unitary slave device.
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal includes:
Bruce et al. (“Bruce”) US 2006/0031615 A1 Feb. 9, 2006
Marks et al. (“Marks”) US 2007/0162592 Al July 12, 2007
Maheshwari et al. WO 2008/0046638 Al Feb. 21,2008
(“Maheshwari”)
REJECTIONS
(1) Claims 1—5, 8, 10, and 11 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over the combination of Bruce and Marks. Final
Act. 2-4.
(2) Claims 6 and 9 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over the combination of Bruce, Marks, and Maheshwari. Final
Act. 4—5.
(3) Claims 13, 14, and 16—20 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over the combination of Bruce, Maheshwari, and
Marks. Final Act. 5—8.
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Application 13/706,911
Our review in this appeal is limited only to the above rejections and
issues raised by Appellant. Arguments not made are waived. See MPEP
§ 1205.02; 37 C.F.R. §§ 41.37(c)(l)(iv) and 41.39(a)(1).
ISSUES
1. Does the Examiner err in finding the combination of Bruce and
Marks teaches or suggests “using a register to program register data to
control whether a first slave device of the plurality of slave devices shares
the slave port with a second slave device of the plurality of slave devices,”
as recited in claim 1 ?
2. Does the Examiner err in finding the combination of Bruce and
Marks teaches or suggests “a register coupled to the bus matrix circuit,” as
recited in claim 8?
3. Does the Examiner err in finding the combination of Bruce,
Maheshwari, and Marks teaches or suggests “the bus matrix circuit is
adapted to cause the processing core to perceive the non-volatile and
volatile memory devices as collectively being a unitary slave device,” as
recited in claim 17?
CONTENTIONS AND DISCUSSION
We disagree with Appellant’s contentions and adopt as our own (1)
the Examiner’s findings and reasoning set forth in the Office Action from
which this appeal is taken (Final Act. 2—7) and (2) the Examiner’s reasoning
set forth in the Examiner’s Answer (Ans. 2-4). We highlight the following
points for emphasis.
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Application 13/706,911
Issue 1 — claim 1
The Examiner finds Marks’ expanded raid system using external slave
discs teaches “using a register to program register data to control whether a
first slave device of the plurality of slave devices shares the slave port with a
second slave device of the plurality of slave devices,” as recited in claim 1.
Final Act. 4 (citing Marks 136). Specifically, the Examiner finds Marks
teaches an “initiator (the claimed ‘master device’) may access a plurality of
target devices (the claimed ‘slave devices’) through a single initiator port
(the port of the expander that directly connects to the initiator device - the
claimed ‘slave port’).” Ans. 2 (citing Marks Fig. 2); see also Final Act. 8
(citing Marks H 23, 34).
Appellant argues “although a given target (drive) may be accessed by
more than one SAS initiator, Marks fails to disclose or suggest that a given
target shares a given expander port with another target.” Appeal Br. 9.
We find Appellant’s argument unpersuasive. Marks’ Figure 2
discloses that each SAS expander 31 provides a single port shared by
multiple slave drives to allow each to be controlled by an initiator such as
server 200. Marks Fig. 2; see also 22—24, Fig. 3. As a further example,
Marks discloses “[a]n ‘expander’ is a device that provides an initiator with
access to additional targets (and vice versa). Expanders provide
functionality similar to that provided by a hub or switch.” Marks 123,
emphases added. Accordingly, we agree with the Examiner’s finding that
Marks teaches controlling a plurality of slave devices to share a single slave
port. Final Act. 4; Ans. 2.
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Appellant further argues “Marks fails to disclose or render obvious
using a register to designate the domains” because “the Examiner’s reliance
on design choice is clearly improper.” Appeal Br. 10.
The Examiner responds
the reliance on design choice is in fact proper. Marks discloses
that a memory is needed in order to store the list of slave
addresses that are allowed in the “zone” (paragraph 0025 - the
direct routing table). Although Marks does not expressly state
that this memory is a register, the examiner maintains that it
would have been obvious to one of ordinary skill in the art to
use a register for faster memory access times (as is known in
the art). “[DJesign choice may be an acceptable rationale for an
obviousness rejection when a claimed product merely arranges
known elements in a configuration recognized as functionally
equivalent to a known configuration.” See In re Kuhle, 526
F.2d 553, 555 (CCPA 1975). In this case, a memory register is
functionally equivalent to any other type of memory in that is
stores data.
Ans. 3.
We find Appellant’s argument unpersuasive. A modification of prior
art teachings may be a matter of design choice unless a proposed change
results in different structure and function. In re Gal, 980 F.2d 717, 719-20
(Fed. Cir. 1992). In this case, Appellant fails to establish any functional or
structural differences between the claimed register and Marks’ high speed
memory. Rather, we agree with the Examiner’s finding that “a memory
register is functionally equivalent to any other type of memory in that [it]
stores data.” Ans. 3. Furthermore, the Examiner has provided reasoning
with rational underpinnings as a reason to modify the teachings of Marks,
namely, “it would have been obvious to one of ordinary skill in the art to use
a register [to obtain] faster memory access times.” Ans. 3; see In re Kahn,
441 F.3d 977, 988 (Fed. Cir. 2006) (“[R]ejections on obviousness grounds
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Application 13/706,911
[require] some articulated reasoning with some rational underpinning to
support the legal conclusion of obviousness”) (cited with approval in KSR
Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). Appellant fails to show
this reasoning is deficient. Appellant also fails to provide any evidence that
substituting Marks’ memory for the claimed register to store data for
controlling the sharing of the slave port would have been uniquely
challenging or difficult for one of ordinary skill in the art. Leapfrog
Enterprises., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir.
2007).
We, thus, sustain the Examiner’s obviousness rejection of claim 1.
Dependent claims 2—6, are not argued separately, and thus, fall with their
respective independent claims. Appeal Br. 12.
Issue 2 — claim 8
The Examiner finds Bruce teaches “a register coupled to the bus
matrix circuit,” as recited in claim 8. Final Act. 5; Ans. 3^4 (citing Bruce
Fig. 4, items 365 and 325 and 149).
Appellant argues “neither Bruce nor Marks discloses or renders
obvious a register that is coupled to a bus matrix.” Appeal Br. 11.
Specifically, Appellant argues
In other words, no plausible reason has been advanced to
explain why, absent hindsight gleaned solely from the present
application, one of ordinary skill in the art would have derived
a register that is coupled to Bruce’s interconnect block 300 (the
alleged bus matrix module) to store data, much less a register
coupled to the interconnect block 300 to store data, where the
register is adapted to control whether a first slave device shares
a slave port with a second slave device.
Appeal Br. 11; see also Reply Br. 3^4.
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As an initial matter, we agree with the Examiner’s finding that
Bruce’s register slice 365 teaches a register, as Appellant appears to note.
See Appeal Br. 11 supra. Appellant, therefore, essentially argues that
Bruce’s register slice 365 does not suggest the claimed register because
register slice 365 stores different data performing different functions than
the claimed register. Reply Br. 4 (“It is entirely unclear how storing a
predicted value in a value prediction register [as taught by Bruce] would
control whether one slave device shares a port with another slave device.”).
We are not apprised of error based on this argument because non­
obviousness cannot be established by attacking references individually when
the rejection is based on a combination of prior art. See In re Merck & Co.,
800 F.2d 1091, 1097 (Fed. Cir. 1986). Here, by arguing that Bruce alone
fails to teach the claimed register, Appellant does not address the rejection as
articulated, in which the Examiner relies on certain combined teachings of
the prior art. See Ans. 3 (citing Marks 125 and finding Marks’ memory
storing the direct routing table teaches a register to control the sharing of a
port, as recited in claim 8).
To the extent Appellant argues the Examiner’s reasoning is based on
hindsight (Appeal Br. 11) we are also not persuaded. Rather than using
hindsight, the Examiner points to specific disclosures in the references that
describe the limitation. See Final Act. 5; Ans. 3^4. We therefore find that
the Examiner’s obviousness conclusion is based on sufficiently articulated
reasoning that overcomes any concerns about hindsight bias. See KSR, 550
U.S. at 418.
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We, thus, sustain the Examiner’s obviousness rejection of claim 8.
Dependent claims 9-11 are not argued separately, therefore we also sustain
the rejection of these claims. Appeal Br. 12.
Issue 3 — claim 17
The Examiner finds Maheshwari suggests “wherein the bus matrix
circuit is adapted to cause the processing core to perceive the non-volatile
and volatile memory devices as collectively being a unitary slave device,” as
recited in claim 17. Final Act. 7 (citing Maheshwari 137).
Appellant argues the cited portion of Maheshwari “merely discusses
ports being ‘configured to interface with certain types of volatile or non­
volatile memory. Appeal Br. 14. Appellant further argues “Maheshwari
merely interfaces with either the SDRAM 68 or the NAND flash memory
70, however. Neither processor 62 nor 64 perceives these memory devices
collectively, i.e., perceives these devices as ‘collectively being a unitary
slave device.’” Reply Br. 4.
We find Appellant’s argument unpersuasive. As the Examiner notes,
Maheshwari indicates “the SDRAM 68 and the NANO flash memory 70 are
shared by the processors 62 and 64 in a transparent fashion.” Ans. 4
(citing Maheshwari 138). Accordingly, we agree with the Examiner’s
finding that “[sjince the processor core 62 is not addressing the memory
devices 68 and 70 individually, the processor core 62 does in fact ‘perceive’
them as a unitary slave device.” Ans. 4.
We, thus, sustain the Examiner’s obviousness rejection of claim 17.
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Appellant argues claim 13 is not obvious over the combination of
Bruce, Marks, and Maheshwari, reciting substantially similar arguments as
those discussed above for claims 8 and 17. Appeal Br. 12—13.
We, thus, sustain the Examiner’s obviousness rejection of claim 13.
Dependent claims 14, 16, and 18—20 are not argued separately, therefore we
also sustain the rejection of these claims.
DECISION
We affirm the Examiner’s decision rejecting claims 1—6, 8—11, 13, 14,
16-20 under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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