Ex Parte LIN

Patent Trial and Appeal Board

Apr 19, 2016

12869910 (P.T.A.B. Apr. 19, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/869,910 08/27/2010
49579 7590 04/20/2016
STERNE, KESSLER, GOLDSTEIN & FOX PLLC
1100 NEW YORK A VENUE, N.W.
WASHINGTON, DC 20005
Shengli LIN
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2875.4890000 8774
EXAMINER
PAPE, ZACHARY
ART UNIT PAPER NUMBER
2835
MAILDATE DELIVERY MODE
04/20/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHENGLI LIN
Appeal2014-003058
Application 12/869,9101
Technology Center 2800
Before JOSEPH L. DIXON, LIJ\.JZY T. 1\1cCi1~RTNEY, and
MELISSA A. RAAP ALA, Administrative Patent Judges
DIXON, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134 from a rejection of claims 1-
22. An oral hearing was held on March 23, 2016. We have jurisdiction
under 35 U.S.C. § 6(b ).
We affirm-in-part.
1 Appellant indicates that the real party in interest is Broadcom Corporation.
(App. Br. 3).
Appeal2014-003058
Application 12/869 ,910
STATEMENT OF CASE
The claims are directed to methods and devices for differential signal
channel length compensation in an electronic system. Claim 1, reproduced
below, is illustrative of the claimed subject matter:
1. A substrate, comprising:
a first metal layer including a first trace and a second trace;
a second metal layer including a ground plane;
a dielectric layer arranged between the first and second
metal layers;
a first solder pad and a second solder pad connected to the
first trace and the second trace respectively; and
a first cutout and a second cutout in the ground plane
corresponding with the first solder pad and the second solder pad
respectively, wherein a length of the second trace is shorter than
a length of the first trace, wherein an open area of the second
cutout is less than an open area of the first cutout, and wherein
the ground plane is a single-layer ground plane.
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Renken
Chao et al.
(hereinafter "Chao")
Wright et al.
(hereinafter "Wright")
Minegishi et al.
(hereinafter "Minegishi")
us 4,603,309
us 4,736,165
US 6,624,729 B2
US 8,040,200 B2
Evidence introduced by Appellant:
2
July 29, 1986
Apr. 5, 1988
Sept. 23, 2003
Oct. 18, 2011
Appeal2014-003058
Application 12/869 ,910
Steinfeld et al. US 7,129,416 Bl Oct. 31, 2006
REJECTIONS
Claims 1-3, 7-13, and 17-20 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Minegishi in view of Renken.
Claims 4---6, 14--16, and 21 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Minegishi in view of Renken and further in view of
Wright.
Claim 22 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Minegishi in view of Renken and further in view of Chao.
ANALYSIS
With respect to independent claims 1, 11, and 21, Appellant presents
the same argument. (App. Br. 10, 18). We select independent claim 1 as the
representative claim for the group and address Appellant's arguments
thereto. With respect to dependent claims 10 and 20, Appellant presents the
same argument. (App. Br. 17-18). We select dependent claim 10 as the
illustrative claim for the group and address Appellant's arguments thereto.
Representative claim 1
With respect to independent claim 1, Appellant argues the Examiner's
interpretation of the claimed "single-layer ground plane" is in error and the
Minegishi reference teaches a two-layer ground plane. (App. Br. 10-11).
Consequently, Appellant maintains Minegishi's two-layer ground plane
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Application 12/869 ,910
cannot constitute the "single-layer ground plane," as recited in independent
claims 1 and 11. (App. Br. 11 ).
Appellant introduces U.S. Patent No. 7,129,416 Bl to Steinfeld as an
exemplary interpretation of the claim terminology "single-layer ground
plane." To reinforce Appellant's proffered argument regarding the
difference between the claimed "single-layer ground plane" and Minegishi' s
two-layer ground plane, Appellant relies on the background of Steinfeld to
define and differentiate between different types of ground planes. (App. Br.
12-14; Reply Br. 3-7).
In response, the Examiner further finds:
Further at [0021] of the present invention written description the
Examiner notes the language, "Printed circuit board 100 contains
at least two surfaces 110 and 120 of dielectric layer 150"
(emphasis added) which again is open ended language. Here the
invention clearly contemplates that more than one ground plane
layer can be present. Indeed nowhere is the Examiner able to
find any language anywhere in the specification that specifically
excludes a printed circuit board which has two ground plane
layers which work in concert with each other to carry a signal.
(Ans. 5).2
While we agree with Appellant that there is a difference between a
single-layer ground plane and a two-layer ground plane, we find that the
Steinfeld further discloses:
In conventional circuit mounting boards (e.g., printed
circuit boards (PCB's)) a ground plane is formed on one or more
layers of the board. Such ground planes can be formed on the
top or bottom surfaces of boards (especially using basic two layer
2 We agree with the Examiner that Appellant has not identified any express
definition of the claim terminology within Appellant's Specification, nor has
Appellant identified any written description support in the originally filed
Specification for the term "single-layer ground plane."
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Application 12/869 ,910
boards). Also, such ground planes can be formed on interior
layers of multi-layer (three or more layers) boards. Such ground
planes are satisfactory for certain purposes, but they impose
certain significant design limitations. For example, they prohibit
the formation of signal traces on the layer containing the ground
plane. On a two-layer board this can be a particularly
cumbersome design limitation because it effectively prevents
circuit structures and electronic components from being formed
on or attached to the ground plane layer.
(Steinfeld col. 1, 11. 18-33). We find Steinfeld discloses that both
single-layer and double-layer ground planes were well-known at the
time of the invention and that artisans of ordinary skill knew and
appreciated the known trade-offs in using single-layer versus two-
layer ground planes. Thus, we agree with Appellant that the Steinfeld
reference identifies a difference between single-layer and a two-layer
ground plane, but Steinfeld 'additionally identifies trade-offs and
motivation for the use of different types of ground planes.
Appellant's argument merely identifies a difference in the number of
ground plane layers utilized by the Minegishi reference, but Appellant
does not identify any difficulty in using a single-layer versus a two-
layer ground plane.
We note that the language of independent claim 1 is directed to
"[a] substrate, comprising." Hence, the claimed invention is directed
to the entire spectrum of uses, voltages, and frequencies. Within this
vast expanse, we find that skilled artisans would have appreciated the
different uses and different fields of endeavor with known trade-offs
which would have been considered in designing a substrate. When
there is a design need or market pressure to solve a problem and there
are a finite number of identified, predictable solutions, a person of
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Application 12/869 ,910
ordinary skill has good reason to pursue the known options within his
or her technical grasp. If this leads to the anticipated success, it is
likely the product not of innovation but of ordinary skill and common
sense. In that instance the fact that a combination was obvious to try
might show that it was obvious under§ 103. KSR Int'l Co. v. Teleflex
Inc., 550 U.S. 398, 421 (2007) (emphasis added).
Appellant's argument that the Minegishi reference teaches only a two-
layer ground plane rather than a single-layer ground plane is not persuasive
because Steinfeld expressly teaches that various ground planes were well-
known to those skilled in the art and "[s]uch ground planes are satisfactory
for certain purposes, but they impose certain significant design limitations."
(Steinfeld col. 1, 11. 18-33)
Appellant has not provided persuasive evidence or argument to show
that modifying Minegishi to use a single layer ground plane was "uniquely
challenging or difficult for one of ordinary skill in the art." See Leapfrog
Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007)
(citing KSR, 550 U.S. at 419). Absent such evidence or argument, we "take
account of the inferences and creative steps that a person of ordinary skill in
the art would employ," and find using a single-layer ground plane was
within the level of ordinary skill in the art. See KSR, 550 U.S. at 418; see
also id. at 421 ("A person of ordinary skill is also a person of ordinary
creativity, not an automaton."); Perfect Web Techs., Inc. v. InfoUSA, Inc.,
587 F.3d 1324, 1329 (Fed. Cir. 2009) (explaining that an obviousness
analysis "may include recourse to logic, judgment, and common sense
available to the person of ordinary skill that do not necessarily require
explication in any reference or expert opinion").
Appellant further contends:
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Application 12/869 ,910
Furthermore, the Office appears to be arguing that the
functionality of Minegishi 's ground plane can be partitioned into
two separated ground planes. However, the term "ground plane"
refers to the aggregate return path provided for currents from
various components of the circuit board. Thus, a simple ground
plane would occupy the entirety of a single layer, and be referred
to as a "single-layer ground plane." More complex return path
designs require more than a single layer to accomplish this, and
are referred to as "two-layer ground planes" and "multi-layer
ground planes." Minegishi 's design is one of those "two layer
ground plane" designs, and therefore Minegishi 's two-layer
ground plane cannot constitute the "single-layer ground plane,"
as recited in independent claims 1, 11 and 21.
(Reply Br. 3). While we agree with Appellant's identification of structural
differences between the Minegishi reference and the claimed invention, m
light of Steinfeld' s teachings, we find Appellant's argument to be
unpersuasive of error in the Examiner's conclusion of obviousness of the use
of the single-layer ground plane rather than a two-layer ground plane.
Appellant further argues that Minegishi does not disclose the claimed
"a first cutout and a second cutout in the ground plane corresponding with
the first solder pad and the second solder pad respectively" and the
Examiner's reliance on In re Kuhle does not remedy this deficiency. (App.
Br. 15-16). The Examiner clarifies that it is the combination of the
Minegishi and Renken references that teaches and suggests this limitation.
(Ans. 15 - 16). The Examiner further clarifies that ln re Kuhle and design
choice was only relied upon in the rejection of claims 10 and 20. (Id.)
Appellant further contends that the Examiner's statement that "there
will inherently be some type of correspondence between the solder pad and
the cutouts as claimed" is a naked assertion with no factual basis to support
it. (Reply Br. 4). We disagree with Appellant and find the breath of
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Application 12/869 ,910
independent claim 1 encompasses any relationship between the cutouts and
solder pads. We agree with the Examiner that there is inherently some type
of spatial relationship between any two physical objects. (Ans. 7).
We have reviewed Appellant's remaining arguments concerning claim
1 and find them unpersuasive in light of the analysis above. Appellant
maintains claims 2, 3, 7-10, 12, 13, and 17-20 depend from independent
claims 1 and 11 and are allowable for that reason. (App. Br. 16-17). We
disagree with Appellant and find claims not specifically argued fall with
representative independent claim 1. Accordingly, we sustain the Examiner's
rejection of claim 1, and we also sustain the Examiner's rejection of
dependent claims 2, 3, 7-9, 12, 13, and 17-19, which are not separately
argued. See 37 C.F.R. § 41.37(c)(l)(iv).
Appellant maintains claims 4---6, 14--16, 21, and 22 depend from
independent claim 1 and are allowable for that reason. (App. Br. 18-19).
We disagree with Appellant and find no deficiency in the base combination
with respect to representative independent claim 1. Accordingly, we sustain
the Examiner's rejection of claims 4---6, 14--16, 21, and 22, which are not
separately argued. See 37 C.F.R. § 41.37(c)(l)(iv).
Claims 10 and 20
Appellant sets forth specific arguments for patentability of dependent
claims 10 and 20. Appellant contends that the Examiner's reliance upon
"design choice" alone is insufficient to show the obviousness of the claimed
vertical alignment feature of dependent claim 10. (App. Br. 16-17).
Specifically, Appellant contends:
However, "design choice" does not constitute the required
disclosure of the "vertical alignment" feature. Locations of
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Application 12/869 ,910
components are not merely mechanical positioning requirements
whereby such locations can be changed on a whim. Instead,
electrical performance, which depends upon location of
components, is crucial to the overall operation of a high speed
printed circuit board layout. For example, electrical performance
includes such things as a consideration of Minegishi 's common-
mode signal (See e.g., Minegishi. Col. 1, Ln. 62-64), and the
pending application's differential signal timing skew - all of
which depend upon location. Despite the crucial impact of
location on the electrical characteristics on the performance of
high speed printed circuit boards, the Office ignores this
important principle by saying that it would be obvious to move
components if required to do so. Put another way, were the
Office to acknowledge this important principle, it would
eviscerate the Office's argument that the recited "vertical
alignment" feature is rendered obvious.
(App. Br. 17).
The Examiner further clarifies that:
With respect to the Appellant's remarks to claim 10 which
recites that the importance of the position of components on a
circuit board (Appeal Brief page 17) the Examiner does not
disagree, however the Examiner respectfully notes that claim 10
is not reciting limitations to the position of components on the
substrate as alleged, rather claim 10 recites limitations to solder
pads and their alignment with the cutouts. Therefore the
Appellant's remarks that "the Office ... [is] saying that it would
be obvious to move components if required to do so" is improper.
Indeed what the Examiner is saying is that it is obvious to place
solder pads anywhere along a trace.
(Ans. 8).
Appellant argues that it is nonobvious to place solder pads anywhere
along a trace because of the reality of multi-gigaHertz circuit board design.
(Reply Br. 4). Appellant contends:
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Application 12/869 ,910
"Specifically, it is not obvious to place solder pads anywhere
along a trace at least because of these signal integrity issues.
Furthermore, even were a circuit board designer able to place
solder pads anywhere along a trace, such an assumption still does
not provide the required disclosure of the recited "vertical
alignment" feature (which recites "wherein the first solder pad
and the second solder pad are vertically aligned with the first
cutout and the second cutout respectively")."
(Reply Br. 4). We agree with Appellant that the Examiner's sweeping
reliance upon "design choice" is too broad. The Examiner has not supported
the reliance upon "design choice" with any underlying factual findings or
line of reasoning. Consequently, we cannot sustain the rejection of
dependent claims 10 and 20.
CONCLUSIONS
Under 35 U.S.C. § 103, the Examiner did not err in rejecting claims
1-9, 11-19, 21, and 22, but the Examiner did err in rejecting claims 10 and
20.
DECISION
For the above reasons, we sustain the Examiner's obviousness
rejection of claims 1-9, 11-19, 21, and 22, and we do not sustain the
Examiner's obviousness rejection of claims 10 and 20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
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Application 12/869 ,910
AFFIRMED-IN-PART
11