Ex Parte Karalar

Patent Trial and Appeal Board

Apr 15, 2016

13250036 (P.T.A.B. Apr. 15, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/250,036 09/30/2011
21906 7590 04/19/2016
TROP, PRUNER & HU, P,C
1616 S. VOSS ROAD, SUITE 750
HOUSTON, TX 77057-2631
FIRST NAMED INVENTOR
Tufan Coskun Karalar
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SIL.0171US (D-11-600-22) 9357
EXAMINER
POOS,JOHNW
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
04/19/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
tphpto@tphm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TUF AN COSKUN KARALAR
Appeal2014-008664
Application 13/250,0361
Technology Center 2800
Before DEBRA K. STEPHENS, JASON V. MORGAN, and
DAVID J. CUTITTA, Administrative Patent Judges.
CUTITTA, Administrative Patent Judge.
DECISION ON APPEAL
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner's Final
Rejection of claims 1-7, 11, 15-17, 19 and20. Claims 1, 11, and 16 are
independent. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
1 According to Appellant, the real party in interest is Silicon Laboratories Inc. (see Appeal Br. 3).
Appeal2014-008664
Application 13/250,036
Invention
Appellant's application relates to a method and apparatus for
controlling a modulus of a programmable divider, including selectively
activating and deactivating cells of the divider. (Spec. iii! 2, 3).
Exemplary Claims
Claims l and 11) reproduced below with key limitations emphasized,
are stated to be exemplary:
1. A method comprising:
controlling a modulus of a programmable divider, the controlling
comprising selectively activating and deactivating a plurality of
cells of the divider, each cell of the plurality of cells being
programmable by an associated at least one programming signal
to cause the cell to divide by one of multiple moduli;
wherein the activating comprises, for at least one of the cells,
configuring an output signal of the cell to exhibit a
predetermined signal state to override a response of the cell to
the associated at least one programming signal when the cell
transitions from a deactivated state to an activated state.
11. An apparatus comprising:
a programmable divider comprising divider cells, at least a subset
of the divider cells being adapted to be selectively activated and
deactivated in synchronization with a first clock signal to
program a modulus of the programmable divider; and
a controller to, in response to a given divider cell of the divider
cells transitioning from a deactivated state to an activated state,
retime a modulus control signal provided by the given divider
cell from being synchronized to the first clock signal to being
synchronized to a second clock signal.
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Application 13/250,036
Rejections
The Examiner rejects claims 1-7, 11, 15-17, 19 and 20 under 35
U.S.C. § 102(b) as being anticipated by Narathong et al. (US 2008/0042699
Al; Feb. 21, 2008). (Final Act. 2-7).
Issues
Did the Examiner err in finding Narathong discloses: (1) "configuring
an output signal of the cell to exhibit a predetermined signal state to override
a response of the cell to the associated at least one programming signal when
the cell transitions from a deactivated state to an activated state," as recited
in representative independent claim 1; and (2) "a controller to, in response to
a given divider cell of the divider cells transitioning from a deactivated state
to an activated state, retime a modulus control signal provided by the given
divider cell from being synchronized to the first clock signal to being
synchronized to a second clock signal," as recited in independent claim 11?
ANALYSIS
Claims 1-7, 16, 17, 19, and 20
With respect to claim 1, we agree with and adopt as our own the
Examiner's findings of facts and conclusions as set forth in the Answer and
in the Action from which this appeal was taken. We have considered
Appellant's arguments, but do not find them persuasive of error. We
provide the following explanation primarily for emphasis.
Appellant contends that "N arathong fails to disclose at least
configuring an output signal of a cell of a divider to exhibit a predetermined
signal state to override a response of the cell to associated programming
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Appeal2014-008664
Application 13/250,036
signal( s) when the cell transitions from a deactivated state to an activated
state." (App. Br. 10). More specifically, Appellant contends "Narathong
fails to disclose, however, that an output signal of its modulus divider stage
(the 'MDS stage 142') exhibits a predetermined signal state to override a
response of the cell to at least one programming signal when the cell
transitions from a deactivated state to an activated state." (Id. at 11 ).
We are not persuaded by Appellant's arguments.
As set forth at paragraphs 40-43 ofNarathong, and as explained by
the Examiner (Final Action, 2; Answer 2), the state of flip flop 162 of
modulus divider stage (MDS) 142 may be used to determine whether to
override a divide-by-3 mode initiated by modulus divisor control signal S[O]
input at input lead 169. That is, flip flop 162 of MDS stage 142 exhibits a
predetermined signal state (a state other than a digital logic low) to override
a response to the cell (by switching from a divide-by-3 mode back to a
divide-by-2 mode) to the associated at least one programming signal (S[O]),
which initially switches MDS stage 142 from a divide-by-2 mode to a
divide-by-3 mode when S[O] transitions the cell from a deactivated state
(S[O]=a digital logic low) to an activated state (S[O]=a digital logic high).
Thus, as the Examiner correctly finds (Final Action, 2; Answer 2),
Narathong discloses configuring an output signal of a cell of a divider to
exhibit a predetermined signal state to override a response of the cell to the
at least one associated programming signal when the cell transitions from a
deactivated state to an activated state because when flip flop 162 of MDS
stage 142 exhibits a state other than a digital logic low, MDS stage 142 is
switched from a divide-by-3 mode back to a divide-by-2 mode thereby
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Appeal2014-008664
Application 13/250,036
overriding a response of the cell to S[O], which causes MDS stage 142 to
switch from a divide-by-2 mode to a divide-by-3 mode. We agree with the
Examiner's findings, which Appellant does not persuasively rebut.
Therefore, we agree with the Examiner that N arathong discloses
"configuring an output signal of the cell to exhibit a predetermined signal
state to override a response of the cell to the associated at least one
programming signal when the cell transitions from a deactivated state to an
activated state," as recited in claim 1.
Accordingly, we sustain he Examiner's 35 U.S.C. § 102(b) rejection
of claim 1, and claims 2-7, which Appellant does not argue separately.
Appellant makes similar arguments with respect to claim 16. (App. Br. 13).
For the reasons discussed above, we also sustain the Examiner's 35 U.S.C.
§ 102(b) rejection of claim 16, and claims 17, 19, and 20, which Appellant
does not argue separately.
Claims 11 and 15
The Examiner relies on paragraph 3 6 of N arathong to disclose "a
controller to ... retime a modulus control signal provided by the given
divider cell from being synchronized to the first clock signal (Sin) to being
synchronized to a second clock signal (Sout)," as recited in claim 11 (Final
Act. 5, emphasis added).
Appellant contends the Examiner erred because "N arathong fails to
disclose retiming a modulus control signal from being synchronized from the
Sin to a[n] Sout clock signal." (App. Br. 13). More specifically, Appellant
argues both stages 157 and 158 ofNarathong's MDS stage 142 are clocked
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Appeal2014-008664
Application 13/250,036
by the Sin clock signal and are, therefore, not retimed to another clock
signal.
We agree that the Examiner fails to establish that Narathong discloses
a modulus control signal that is retimed to be synchronized to a different
clock signal because the Examiner fails to establish that Sin and Sout are in
fact timed to different clock signals.
The Examiner further relies upon the modulus divisor control signal
output by 22-bit Sigma Delta Mod 133 of FIG. 3, to disclose the controller
as recited in claim 11. More specifically, the Examiner's Answer asserts
that "modulus divisor control signal is retimed or adjusted from the first
clock signal Sin by the SDM output, which is generated from the second
clock signal Sout." (Ans. 3).
We disagree with the Examiner's finding because FIG. 3 of
Narathong illustrates that 1\1odulus Divisor Control Signals are provided by
the adder to the multi-modulus divider 131 and therefore, we are not
persauded Narathong discloses "a modulus control signal provided by the
given divider cell" (emphasis added), as recited in claim 11.
Accordingly, we cannot sustain the Examiner's 35 U.S.C. § 102(b)
rejection of claim 11, and of dependent claim 15, which contains the same
disputed recitations.
DECISION
We affirm the Examiner's decision rejecting claims 1-7, 16, 17, 19
and 20.
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Application 13/250,036
We reverse the Examiner's decision rejecting claims 11 and 15.
AFFIRMED-IN-PART
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