Ex Parte Jang et al

Patent Trial and Appeal BoardApr 27, 2018

14168112 (P.T.A.B. Apr. 27, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 14/168,112 01/30/2014 29371 7590 05/01/2018 CANTOR COLBURN LLP - IBM FISHKILL 20 Church Street 22nd Floor Hartford, CT 06103 FIRST NAMED INVENTOR Linus Jang UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. FIS920130241US1 9031 EXAMINER NGUYEN, SOPHIA T ART UNIT PAPER NUMBER 2822 NOTIFICATION DATE DELIVERY MODE 05/01/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): usptopatentmail@cantorcolbum.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte LINUS JANG, SIV ANANDA K. KANAKASABAP ATHY, SANJA Y C. MEHTA, SOON-CHEON SEO, and RAGHA V ASIMHAN SREENIV ASAN Appeal2017-005044 Application 14/168,112 Technology Center 2800 Before CATHERINE Q. TIMM, WHITNEY N. WILSON, and JENNIFER R. GUPTA, Administrative Patent Judges. TIMM, Administrative Patent Judge. DECISION ON APPEAL 1 1 In explaining our Decision, we cite to the Specification of January 30, 2014 (Spec.), Final Office Action of February 5, 2016 (Final Act.), Appeal Brief of October 20, 2016 (Appeal Br.), Examiner's Answer of December 1, 2016 (Ans.), and Reply Brief of February 1, 2017 (Reply Br.). Appeal2017-005044 Application 14/168,112 STATEMENT OF THE CASE Pursuant to 35 U.S.C. Â§ 134(a), Appellants2 appeal from the Examiner's decision to reject claims 1, 2, 4--10, and 12-15. We have jurisdiction under 35 U.S.C. Â§ 6(b). We AFFIRM. The claims are directed to a method of forming a semiconductor device that involves forming dummy gate elements from a dielectric material such as boron carbide (BC), carbon (C), silicon dioxide (Si02), or a silicon boron carbide material that contains nitrogen (SiB:C(N)). Claim 1 is illustrative: 1. A method of fabricating a semiconductor device, the method comprising: forming at least one semiconductor fin on a semiconductor substrate; forming an etch stop layer on an upper surf ace of the at least one semiconductor fin; forming a plurality of gate formation layers on the etch stop layer and the substrate, the plurality of gate formation layers including a dummy gate layer formed from a dielectric material; patterning the plurality of gate formation layers to form a plurality of dummy gate elements on the etch stop layer, each dummy gate element formed from a material selected from a group comprising of boron carbide (BC), carbon (C), silicon dioxide (Si02), and a silicon boron carbide material that contains nitrogen (SiB:C(N)); 2 Appellants are the Applicants, International Business Machines Corporation and GLOBALFOUNDERIES, Inc., which, according to the Brief, are the real parties in interest. Appeal Br. 2. 2 Appeal2017-005044 Application 14/168,112 depositing a spacer layer that conforms with an outer surface of each dummy gate element; etching the spacer layer to form a spacer on each sidewall of the dummy gate elements and etching a portion of the etch stop layer located between each dummy gate element to expose a portion of the semiconductor fin; and depositing a contact dielectric layer that fills a void between the spacers, and covers an outer surface of the spacers and an upper portion of the dummy gate elements, and performing a planarization process selective to one of boron carbide (BC), carbon (C), silicon dioxide (Si02), and a silicon boron carbide material that contains nitrogen (SiB:C(N)) such that [sic, the] dummy gate element is used as an etch stop layer so as [sic, to] form an upper surface of the contact dielectric layer flush with an upper surface of each spacer and an upper surface of each dummy gate element. Appeal Br. 12 (claims appendix) (emphasis added). The Examiner maintains the following rejections: A. The rejection of claims 12-15 under 35 U.S.C. Â§ l 12(b) as indefinite; B. The rejection of claims 1 and 2 under 35 U.S.C. Â§ 103 as obvious over Huang3 in view ofDoyle4 ; C. The rejection of claims 4--7 under 35 U.S.C. Â§ 103 as obvious over Huang in view of Doyle and further in view of Ting5; D. The rejection of claim 8 under 35 U.S.C. Â§ 103 as obvious over Huang in view of Doyle and further in view ofLin6; and 3 Huang et al., US 2014/0239354 Al; Aug. 28, 2014 ("Huang"). 4 Doyle et al., US 2007/0152266 Al; July 5, 2007 ("Doyle"). 5 Ting et al., US 2009/0186475 Al, published July 23, 2009. 6 Lin et al., US 8,053,323 Bl, issued Nov. 8, 2011. 3 Appeal2017-005044 Application 14/168,112 E. The rejection of claims 9, 10, and 12-15 under 35 U.S.C. Â§ 103 as obvious over Huang in view of Doyle and Lin and further in view of Goto 7. OPINION Indefiniteness Appellants do not address the Examiner's rejection of claims 12-15 under 35 U.S.C. Â§ 112(b) as indefinite. Appeal Br. 5-11. Thus, we summarily affirm this rejection. Obviousness The rejections and arguments give rise to two issues, one for claim 1 and another for claim 8, which is of different scope than claim 1. Compare claim 1, with claim 8; compare also Final Act. 3-11, and Ans. 12-14, with Appeal Br. 5-11, and Reply Br. 2-8. Thus, we focus on the rejections of claims 1 and 8. Claim 1 The Examiner finds that Huang teaches the claimed method except that the dummy gates are not disclosed as formed from a material selected from the group recited in claim 1. Final Act. 3--4. Huang discloses using, for example, polysilicon as the dummy gate material, but suggests that other materials having a high etching selectivity from the etching of STI regions 52 may also be used. Huang i-f 25. The Examiner concludes that it would 7 Goto et al., US 2014/0070328 Al, published Mar. 13, 2014. 4 Appeal2017-005044 Application 14/168,112 have been obvious to use Si02 dielectric material as the dummy gate material because Doyle discloses Si02 as a suitable alternative material for dummy gates. Final Act. 4. Appellants do not dispute the Examiner's finding of a suggestion to use Si02 as an alternative material in Huang's dummy gate, instead Appellants contend that because Huang fails to teach using Si02 as the dummy gate material, Huang also fails to teach performing a planarization process that is selective to Si02 such that the dummy gate element is used as an etch stop layer. Appeal Br. 8. According to Appellants, Huang describes using a separate, individual etch stop layer 77 that encapsulates the dummy gates 68; it does not teach using the dummy gates 68 as an etch stop layer. Appeal Br. 8-9. The issue arising is: Have Appellants identified a reversible error in the Examiner's finding that Huang teaches performing a planarization process selective to Huang's dummy gate element "such that dummy gate element is used as an etch stop layer so as form an upper surface of the contact dielectric layer flush with an upper surface of each spacer and an upper surface of each dummy gate element" as recited in claim 1? Appellants have not identified such an error. First, we point out that claim 1 is not, in fact, limited to using boron carbide (BC), carbon (C), silicon dioxide (Si02), or a silicon boron carbide material that contains nitrogen (SiB:C(N)) in the dummy gate elements. Claim 1 recites that the dummy gate elements are formed "from a material selected from a group comprising of boron carbide (BC), carbon (C), silicon dioxide (Si02), and a silicon boron carbide material that contains nitrogen (SiB:C(N))" (emphasis added). "[C]omprising" opens the group to other 5 Appeal2017-005044 Application 14/168,112 materials. The extent to which "comprising" opens the claim to other materials is not perfectly clear to us, but we do not have a rejection under indefiniteness to review. In any event, the Examiner finds Doyle teaches using Si02 as a dummy gate element material and Appellants do not dispute either this finding or the Examiner's finding of a reason for using Si02 in Huang's dummy gate elements. Thus, although the scope of materials included is unclear, we need not consider this scope question further in this appeal. Second, we consider the limiting effect of the recitation "such that [sic, the] dummy gate element is used as an etch stop layer" on the method of claim 1. We note that the Specification does not contain this language. Instead, the Specification describes the planarization process as follows: At operation 2118, a portion of contact dielectric layer and a portion of the spacers are recessed using, for example, a chemical mechanical planarization (CMP) process. The planarization process may stop on the upper surface of the dummy gate elements such that the upper surface of the contact dielectric layer is flush with the upper surfaces of the dummy gate elements. Spec. i-f 56. A comparison of Figures 10 and 11 shows the structure before planarization (Fig. 10) and after planarization (Fig. 11 ). Planarization stops on the upper surface of the dummy gate elements 222 so the upper surface of the contact dielectric layer 232 is flush with the upper surfaces of the dummy gate elements 222. Spec. i-f 45. The Specification does not describe any other step as a step of using the dummy gate element as an etch stop. Thus, we interpret the phrase "such that [the] dummy gate element is used as an etch stop layer so as [sic, 6 Appeal2017-005044 Application 14/168,112 to] form an upper surface of the contact dielectric layer flush with an upper surface of each spacer and an upper surface of each dummy gate element" as referring to the step of performing CMP so planarization stops on the upper of the dummy gate elements. Third, we consider the teachings of Huang. Huang, like Appellants, deposits dummy gate material and planarizes by CMP. Huang i-f 25. Before planarizing, Huang deposits an etch stop layer 77 as well as a contact dielectric layer (Inter Layer Dielectric (ILD) 78) over the dummy gate elements 68. Huang i-f 32, Fig. 9A. But the presence of the etch stop layer does not preclude the dummy gate elements 68 as acting as etch stop layers. In fact, Huang etches away the etch stop layer 77 from the top of the dummy gates 68. Huang i-f 33, Fig. lOA. And Huang, like Appellants, stops etching when the top surfaces of the dummy gate elements 68 are exposed. Compare Huang i-f 33, with Spec. i-fi-145, 56. Thus, a preponderance of the evidence supports the Examiner's finding that Huang's planarization uses the dummy gate elements as an etch stop layer as required by claim 1. Appellants have not identified a reversible error in the Examiner's finding that Huang teaches performing a planarization process selective to Huang's dummy gate element "such that dummy gate element is used as an etch stop layer so as form an upper surface of the contact dielectric layer flush with an upper surface of each spacer and an upper surface of each dummy gate element" as recited in claim 1. When using Si02 as the dummy gate element material per the teachings of Doyle, the ordinary artisan would have stopped etching as taught by Huang. Appellants provide no convincing evidence or argument that the ordinary skilled artisan would not have been 7 Appeal2017-005044 Application 14/168,112 capable of selecting the materials of the layers to achieve the flush surface desired by Huang. Claim 8 Appellants' sole argument in the Appeal Brief regarding the rejection of claim 8 is that the Examiner provided no evidence that the ordinary artisan would replace Huang's polysilicon dummy gate 68 with a dummy gate formed from dielectric material without first learning of Appellants' teachings. Appeal Br. 10. But Doyle provides evidence that it was known in the art to form dummy gates from dielectric materials such as silicon nitride and silicon dioxide (Si02). Doyle i-fi-f 15, 20. In the Reply Brief, Appellants contend that one would not have formed the dummy gate of dielectric material because it would destroy the ability to etch the dummy gate layer with respect to the dielectric STI region 52. Reply Br. 7. This argument is based on a teaching in Huang that materials having a high etch selectivity from the etching of STI regions 52 may be used to form the dummy gate. Huang i1 25. But there is no evidence that the ordinary artisan would not know how to accomplish the desired selectivity with dielectric materials. To the contrary, Huang suggests using silicon dioxide to form the STI regions, but also suggests that other dielectric materials can be used. Huang i-f 18. Doyle recognizes the issue of selectivity and indicates that selectivity can be achieved even between two very similar dielectric materials, i.e., between carbon-doped silicon nitride dummy gates and carbon-doped silicon nitride spacers containing other dopants. Doyle i-fi-f 19--20. Thus, the prior art provides evidence that the ordinary artisan understood how to achieve the desired selectivity between dielectric materials. 8 Appeal2017-005044 Application 14/168,112 Appellants have not identified a reversible error in the Examiner's finding that Doyle teaches using dielectric materials in dummy gate elements and the Examiner's finding of a suggestion to make the combination. CONCLUSION In summary: 12-15 Â§ 112(b) 12-15 1, 2 Â§ 103 Ruan , Do le 1, 2 4--7 Â§ 103 Huang, Doyle, 4--7 Tin 8 Â§ 103 Huang, Doyle, 8 Lin 9, 10, 12-15 Huang, Doyle, 9, 10, 12-15 Lin, Goto Summary 1, 2, 4--10, 12-15 DECISION The Examiner's decision is affirmed. TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal maybe extended under 37 C.F.R. Â§ 1.136(a)(l). AFFIRMED 9