Ex Parte Hutchins et al

Patent Trial and Appeal BoardApr 22, 2016

10846208 (P.T.A.B. Apr. 22, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 10/846,208 05/14/2004 Edward A. Hutchins 45594 7590 04/25/2016 NVIDIA C/O MURABITO, HAO & BARNES LLP TWO NORTH MARKET STREET THIRD FLOOR SAN JOSE, CA 95113 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. NVID-P001250 9399 EXAMINER RICHER, JONI ART UNIT PAPER NUMBER 2611 MAILDATE DELIVERY MODE 04/25/2016 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte EDWARD A. HUTCHINS, BRIAN K. ANGELL, JIM BATTLE, and PAUL KIM Appeal2014-006662 Application 10/846,208 Technology Center 2600 Before CARLA M. KRIVAK, HUNG H. BUI, and JOHN F. HORVATH, Administrative Patent Judges. BUI, Administrative Patent Judge. DECISION ON APPEAL Appellants 1 seek our review under 35 U.S.C. Â§ 134(a) of the Examiner's Final Rejection of claims 1, 3-13, and 15--43, which are all the claims pending in this appeal. Claims 2 and 14 are cancelled. We have jurisdiction under 35 U.S.C. Â§ 6(b ). We AFFIRM.2 1 According to Appellants, the real party in interest is Nvidia Corp. App. Br. 1 2 Our Decision refers to Appellants' Appeal Brief filed Jan. 22, 2014 ("App. Br."); Reply Brief filed May. 20, 2014 ("Reply Br."); Examiner's Answer mailed Mar. 20, 2014 ("Ans."); Final Office Action mailed Apr. 22, 2013 ("Final Act."); and original Specification filed May 14, 2004 ("Spec."). Appeal2014-006662 Application 10/846,208 STATEMENT OF THE CASE Appellants' Invention Appellants' invention relates to a method of processing pixels in a graphics pipeline. Spec. i-f 6; Abstract. Claims 1, 13, 24, and 34 are independent. Claims 1 and 24 are illustrative of Appellants' invention, as reproduced below: 1. A method of processing pixels in a graphics pipeline compnsmg: detecting screen coincidence between a first pixel and a second pixel in said graphics pipeline wherein said first pixel has entered a downstream pipeline portion of said graphics pipeline but has not yet completed processing within said graphics pipeline; in response to said detecting said coincidence, stalling propagation of said second pixel to said downstream pipeline portion until said first pixel completes processing within said graphics pipeline; and in advance of a data fetch stage of said downstream pipeline portion obtaining data for said second pixel, issuing an instruction to invalidate a data cache associated with said data fetch stage and wherein said data cache is invalidated upon said second pixel entering said data fetch stage. 24. A method of processing pixels in a graphics pipeline compnsmg: recording encoded screen positions of pixels processed at an upstream stage of said graphics pipeline, said recording performed to detect screen coincidence between a first pixel and a second pixel in said graphics pipeline wherein said first pixel has entered a downstream pipeline portion of said graphics pipeline but has not yet completed processing within said graphics pipeline; and 2 Appeal2014-006662 Application 10/846,208 sending a message to said upstream stage identifj;ing said first pixel in response to said first pixel having completed processing within said graphics pipeline, said sending performed by a downstream stage of said downstream pipeline portion. App. Br. 33, 39 (Claims Appx) (disputed limitation in italics). Hetherington Schlapp Buck-Gengler Reed Coon Parsons Kim Melvin Evidence Considered US. 5,285,323 US. 5,579,473 US. 5,777,628 US. 6,542,971 Bl US. 6,604, 188 B 1 US. 6,731,288 B2 US. 2004/0246260 Al US. 7,257,814 Bl Examiner's Rejections Feb. 8, 1994 Nov. 26, 1996 July7, 1998 Apr. 1, 2003 Aug. 5, 2003 May4, 2004 Dec. 9, 2004 Aug. 14, 2007 (1) Claims 1, 4--8, 11, 13, and 16-20 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Schlapp and Coon. Final Act. 9- 15; Ans. 2-8. (2) Claims 3 and 15 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Schlapp, Coon, and Kim. Final Act. 15; Ans. 8-9. (3) Claims 9-10 and 21-22 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Schlapp, Coon, and Buck-Gengler. Final Act. 16-17; Ans. 9-10. (4) Claim 12 stands rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Schlapp, Coon, Melvin, and Hetherington. Final Act. 17- 18; Ans. 11-12. 3 Appeal2014-006662 Application 10/846,208 (5) Claim 23 stands rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Schlapp, Coon, and Melvin. Final Act. 18-19; Ans. 12. (6) Claims 24, 25, 27, 28, 31-35, 37, 38, and 41--43 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Schlapp and Parsons. Final Act. 19-24; Ans. 12-18. (7) Claims 26 and 36 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Schlapp, Parsons, and Melvin. Final Act. 24; Ans. 18. (8) Claims 29 and 39 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Schlapp, Parsons, and Buck-Gengler. Final Act. 25; Ans. 18-19. (9) Claims 30 and 40 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Schlapp, Parsons, and Reed. Final Act. 25-26; Ans. 19. Issue on Appeal Based on Appellants' arguments, the dispositive issue on appeal is whether the Examiner's combination of Schlapp and Coon teaches or suggests the disputed limitations: and in advance of a data fetch stage of said downstream pipeline portion obtaining data for said second pixel, issuing an instruction to invalidate a data cache associated with said data fetch stage and wherein said data cache is invalidated upon said second pixel entering said data fetch stage sending a message to said upstream stage identifying said first pixel in response to said first pixel having completed processing within said graphics pipeline, said sending performed by a downstream stage of said downstream pipeline portion 4 Appeal2014-006662 Application 10/846,208 as recited in Appellants' independent claims 1 and 24, respectively, and similarly recited in claims 13 and 34. App. Br. 12-19, 23-29; Reply Br. 14-- 19 (emphasis added). ANALYSIS Â§103(a) Rejection of Claims 1, 4-8, 11, 13, and 16--20 based on Schlapp and Coon In support of the rejection of independent claims 1 and 13, the Examiner finds Schlapp discloses a method of processing pixels in a graphics pipeline except for "issuing an instruction to invalidate a data cache associated with said data fetch stage." Final Act. 9-10 (citing Schlapp 3 :40- 45, 12: 17-35, 17:39---65, 18:21-24). The Examiner relies on Coon for teaching the missing feature to support the conclusion of obviousness. Id. at 10-11 (citing Coon 12:43---63). Appellants contend Coon's sequence of events includes: (1) issuing an invalidation (INV AL) instruction to invalidate a data cache; (2) detecting an INV AL instruction; (3) stalling the pipeline; and ( 4) accessing the cache to invalidate the appropriate cache line. App. Br. 18. Accordingly, Appellants argue that Coon does not teach issuing an invalidation instruction to invalidate a data cache based on stalling, and Coon, therefore, teaches away from the claimed invention. App. Br. 14--16; Reply Br. 15 (emphasis added). We do not find Appellants' arguments persuasive. Rather, we find the Examiner has provided a comprehensive response to Appellants' arguments supported by a preponderance of evidence. Ans. 19-23. As such, we adopt the Examiner's findings and explanations provided therein. Id. As correctly 5 Appeal2014-006662 Application 10/846,208 recognized by the Examiner, claims 1 and 13 only recite "issuing an instruction to invalidate a data cache associated with said data fetch stage and wherein said data cache is invalidated upon said second pixel entering said data fetch stage." Id. at 21. Claims 1 and 13 do not recite issuing an instruction to invalidate a data cache based upon the second pixel entering the data fetch stage; rather the claims recite invalidating the data cache based upon the second pixel entering the data fetch stage. Id. That is, the data cache is invalidated after the instruction to validate is issued, and when the second pixel enters the data fetch stage. Contrary to Appellants' arguments, Coon teaches issuing an instruction to invalidate a data cache, and invalidating the data cache based upon a subsequent stall. Id. at 21 (citing Coon 12:43-53). Because "Coon teaches invalidating data cache based upon stalling," and Schlapp teaches that "when a second pixel enters a data fetch stage, the second pixel is stalled," we agree with the Examiner that the combination of Schlapp and Coon teaches or suggests issuing an instruction to invalidate a data cache (Coon 12:43--46) associated with the data fetch stage (Schlapp 17:49---65), wherein the data cache is invalidated upon the second pixel entering the data fetch stage in the manner recited in claims 1 and 13. Id. at 22 (citing Coon 12:49-53; and Schlapp 17:39---65). As such, Coon does not teach away from the claimed invention. For the reasons set forth above, Appellants have not persuaded us of Examiner error. Accordingly, we sustain the Examiner's obviousness rejection of independent claims 1 and 13, and their respective dependent claims 3-12 and 15-23, which Appellants do not argue separately. App. Br. 20. 6 Appeal2014-006662 Application 10/846,208 Â§103(a) Rejection of Claims 24-25, 27-28, 31-35, 37-38, and 41--43 based on Schlapp and Parsons In support of the rejection of independent claims 24 and 34, the Examiner finds Schlapp discloses a method of processing pixels in a graphics pipeline by "recording encoded screen positions of pixels processed at an upstream stage of said graphics pipeline, said recording performed to detect screen coincidence between a first pixel and a second pixel in said graphics pipeline wherein said first pixel has entered a downstream pipeline portion of said graphics pipeline but has not yet completed processing within said graphics pipeline." Final Act. 19 (citing Schlapp 17:32---65, 18:36---61). The Examiner acknowledges Schlapp does not teach that the downstream stage indicates to the upstream stage the pixel has completed processing by sending a message. Id. The Examiner relies on Parsons for teaching the missing feature to support the conclusion of obviousness. That is, the Examiner finds it would have been obvious to modify Schlapp so the downstream stage indicates to the upstream stage the pixel has completed processing by sending a message because Parsons teaches messages are needed in order to communicate between stages of a pipeline. Id. at 20 (citing Parsons 16:55-17:6). Appellants argue: (1) Schlapp does not teach "a downstream stage [that] indicates to an upstream stage that a pixel has completed processing"; and (2) Parsons does not teach "sending a message to an upstream stage identifying a first pixel in response to the first pixel having completed processing within the graphics pipeline, and the sending is performed by a downstream stage of the downstream pipeline portion" and, as such, (3) 7 Appeal2014-006662 Application 10/846,208 Parsons teaches away from the claimed invention, i.e., from identifying a first pixel in response to the first pixel having completed processing within the graphics pipeline. App. Br. 24--28; Reply Br. 16-19. We do not find Appellants' arguments persuasive. Rather, we find the Examiner has provided a comprehensive response to Appellants' arguments supported by a preponderance of evidence. Ans. 23-26. As such, we adopt the Examiner's findings and explanations provided therein. Id. As correctly recognized by the Examiner, Schlapp already teaches a downstream stage indicating to an upstream stage that a pixel has completed processing. Ans. 23 (citing Schlapp 17:32---65, 18:36---61). As a secondary reference, Parsons is merely relied upon to show the indicating is performed by "sending a message" from one stage to another stage of the pipeline. Id. at 25-26; see also Final Act. 19-20. One cannot show non-obviousness by attacking references individually when the rejection is based on a combination of references. In re Keller, 642 F.2d 413, 425 (CCPA 1981). "The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference .... Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art." Keller, 642 F.2d at 425. Based on the combined teachings of Schlapp and Parsons, we agree with the Examiner that Schlapp teaches a downstream stage indicates to an upstream stage a pixel has completed processing, and such an indication can be in the form of a "message" as disclosed by Parsons. Ans. 26. For the reasons set forth above, Appellants have not persuaded us of Examiner error. Appellants' provided no persuasive evidence supporting their assertion that Parsons teaches away from Appellants' claimed 8 Appeal2014-006662 Application 10/846,208 invention. Accordingly, we sustain the Examiner's obviousness rejection of independent claims 24 and 34, and their respective dependent claims 25-33 and 35--43, which Appellants do not argue separately. CONCLUSION On the record before us, we conclude that Appellants have not demonstrated the Examiner erred in rejecting claims 1, 3-13, and 15--43 under 35 U.S.C. Â§ 103(a). DECISION As such, we AFFIRM the Examiner's Final Rejection of claims 1, 3- 13, and 15--43. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. Â§ 1.136(a)(l )(iv). AFFIRMED 9