Ex Parte Hu et al

Patent Trial and Appeal BoardAug 17, 2017

12774558 (P.T.A.B. Aug. 17, 2017)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/774,558 05/05/2010 Hsien-Pin Hu TSM10-0040 8261 43859 7590 08/21/2017 SLATER MATSIL, LLP/TSMC 17950 PRESTON ROAD, SUITE 1000 DALLAS, TX 75252 EXAMINER MAI, ANH D ART UNIT PAPER NUMBER 2829 NOTIFICATION DATE DELIVERY MODE 08/21/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing @ slatermatsil. com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte HSIEN-PIN HU, CHEN-HUA YU, MING-FA CHEN, JING-CHEN LIN, JIUN REN LAI, and YUNG-CHI LIN Appeal 2017-001450 Application 12/774,558 Technology Center 2800 Before ROMULO H. DELMENDO, KAREN M. HASTINGS, and JAMES C. HOUSEL, Administrative Patent Judges. PER CURIAM. DECISION ON APPEAL Appellants1 seek our review under 35 U.S.C. § 134 of the Examiner’s final decision rejecting claims 1, 26, and 282 under 35 U.S.C. § 103(a) as obvious over the combination of Echigo et al. (US 6,274,821 Bl, issued Aug. 14, 2001) (“Echigo”) and Savastiouk et al. (US 7,049,170 B2, issued May 23, 2006) (“Savastiouk ‘170”); rejecting claims 2, 3, and 17—20 under 1 Taiwan Semiconductor Manufacturing Company, Ltd. was identified as the real party in interest (Appeal Br. 2). 2 Claims 4—8 have been withdrawn from consideration. Appeal 2017-001450 Application 12/774,558 35 U.S.C. § 103(a) as obvious over the combination of Echigo and Savastiouk ‘170 and further in view of Higashi et al. (US 2004/0262735 Al, published Dec. 30, 2004) (“Higashi”); and rejecting claims 21—25 under 35 U.S.C. § 103(a) as obvious over the combination of Higashi in view of Savastiouk et al. (US 7,241,641 B2, issued July 10, 2007) (“Savastiouk ‘641”).3 We have jurisdiction over the appeal under 35 U.S.C. § 6(b). We AFFIRM-IN-PART. Claim 1 is representative of the claimed invention: 1. A device comprising: an interposer substantially free from integrated circuit devices, wherein the interposer comprises: a substrate having a first side and a second side opposite to the first side; a plurality of through-substrate vias (TSVs) in the substrate, wherein the TSVs protrude from the first side and the second side of the substrate and are completely filled with a conductive material; a first interconnect structure overlying the first side of the substrate, the first interconnect structure comprising a first dielectric layer and a first redistribution line disposed within the first dielectric layer, wherein the first redistribution line is spaced apart from the first side of the substrate and physically contacts at least one of the plurality of TSV s protruding from the first side of the substrate, wherein the first side of the substrate facing the first dielectric layer is free from conductive material formed thereon; and a second interconnect structure overlying the 3 Appellants refer to Savastiouk ‘641 as Savastiouk ‘170 at pages 7, 10, and 13—14 of the Appeal Brief and page 3^4 of the Reply Brief. This appears to be a typographical error. The Examiner cites Savastiouk ‘641 in the rejection of claims 21—25 (Final Act. 7). 2 Appeal 2017-001450 Application 12/774,558 second side of the substrate, the second interconnect structure comprising a second dielectric layer and a second redistribution line disposed within the second dielectric layer, wherein the second redistribution line is spaced apart from the second side of the substrate and physically contacts at least one of the plurality of TSV s protruding from the second side of the substrate, wherein the second side of the substrate facing the second dielectric layer is free from conductive material formed thereon; a first die bonded onto the first interconnect structure; and a second die bonded to the second interconnect structure through a first plurality of recessed under-bump metallurgy (UBM) layers, wherein at least one of the first dielectric layer or the second dielectric layer comprises an oxide, an oxynitride, or a combination thereof. (Emphasis added). ANALYSIS Rejection over Echigo and Savastiouk ‘170 Claims 1, 26, and 28 are rejected under 35 U.S.C. § 103(a) as obvious over Echigo in view of Savastiouk. Appellants present arguments that mainly focus on independent claim 1 (see Appeal Br., Reply Br. generally). We have reviewed each of Appellants’ arguments for patentability. Having done so, we determine that a preponderance of the evidence supports the Examiner’s determination that the claimed subject matter of representative claim 1 is unpatentable within the meaning of § 103. Thus, we sustain the Examiner’s rejection for essentially those reasons expressed in the Final Action and Answer, including the Examiner’s Response to Argument section, and we add the following primarily for emphasis. 3 Appeal 2017-001450 Application 12/774,558 Echigo discloses a multi-layered printed circuit board including a core substrate 1 and lamination parts 2, 3 arranged on opposite sides of the substrate l,4 as shown in Figure 1, which is reproduced below. FIG. I Figure 1 depicts a cross-sectional view of an electronic device. Each lamination part includes three resist layers (e.g., F1r, F2r, and F3r for lamination part 2) and three insulation layers (e.g., Eli, F2i, and F3i for lamination part 2) (Echigo 3:17—33). Echigo discloses that at least the first resist layer L1R of lamination part 2, the first insulation layer Lf of lamination part 2, the sixth insulation layer L6i of lamination part 3, the sixth 4 Echigo 3:7-12, 17-33. 4 Appeal 2017-001450 Application 12/774,558 resist layer L6r of lamination part 3, a soldering resist layer 13, and a soldering resist layer 17 can be made of a resin material that imparts shock resistance {id. 3:58—62). As shown in Figure 1 above, these layers are the portions of the circuit board structure to which devices 8, 9, 14 are mounted. The Examiner finds that the lamination parts 2, 3 function as first and second dielectric layers of an interposer, as recited in claim 1 (Final Act. 3). The Examiner finds Echigo does not disclose that layers of the lamination parts can be made of an oxide, oxynitride, or combination thereof, as recited in claim 1 {id. at 4). Savastiouk ‘170 discloses an integrated circuit package structure including an interposer 120 having a dielectric layer 144 that can be made of a photoimageable material (Savastiouk ‘170 11:16—19 (emphasis omitted)). Savastiouk ‘170 further discloses that “[s]ome or all of dielectric layers 144 can be silicon dioxide, photosensitive benzocyclobutene (BCB), polybenzoxazole (PBO), or other materials” {id. 5:53—56) (emphasis omitted). Therefore, Savastiouk ‘170 supports the Examiner’s findings and demonstrates it was known in the art to use an oxide (i.e., silicon dioxide) in a resist layer of an interposer {see Ans. 3). Appellants’ main argument is there would have been a lack of reason to modify Echigo in view of Savastiouk ‘ 170 so “at least one of the first dielectric layer or the second dielectric layer comprises an oxide, an oxynitride, or a combination thereof,” as recited in claim 1 (Appeal Br. 11— 13; Reply Br. 2—3). Specifically, Appellants contend Echigo is directed to the use of a resin material that exhibits high thermal shock resistance and drop shock resistance, which must fulfill certain conditions to realize Echigo’s invention, and this material is used in its lamination parts (Appeal 5 Appeal 2017-001450 Application 12/774,558 Br. 12). In view of this, Appellants assert Echigo and Savastiouk ‘170 do not disclose or suggest that dielectric layers of Savastiouk ‘170 would fulfill the requirements for the high thermal shock resistance and drop shock resistance desired by Echigo (id.). Therefore, according to Appellants, one of ordinary skill in the art would not have substituted the dielectric material of Savastiouk ‘ 170 for the high thermal shock resistance and drop shock resistance resin material of Echigo or would not have had a reasonable expectation of success for such a substitution (id.). These arguments are unpersuasive. Echigo discloses that at least one outer layer insulation or resist layer of the lamination parts 2, 3 (with respect to the substrate 1), the soldering resist layer 13, and the soldering resist layer 17 is made of the resin material that imparts shock resistance (Echigo 3:58— 62). Therefore, other layers of the lamination parts 2, 3 (e.g., resist layers L2r, L3r, L4r, and L5r) may be made of other materials, such as the oxide disclosed by Savastiouk ‘170. Moreover, the disclosure of Echigo encompasses embodiments in which none of the layers of the lamination parts 2, 3 is made of the shock resistant resin material (e.g., solder resist layer 13 and/or soldering resist layer 17 may be made of the resin disclosed by Echigo but none of the resist layers of the lamination parts 2, 3). As a result, one of ordinary skill in the art would have had a reasonable expectation of success to modify Echigo to use resist layers made of an oxide, as disclosed by Savastiouk ‘170, and Appellants’ arguments do not persuade us that modifying Echigo in view of Savastiouk ‘170 would have rendered Echigo unsuitable for its intended purpose. In addition, claim 1 recites that “at least one of the first dielectric layer or the second dielectric layer comprises an oxide, an oxynitride, or a 6 Appeal 2017-001450 Application 12/774,558 combination thereof.” As a result, claim 1 permits the dielectric layer of an interposer to include other materials besides an oxide, oxynitride, or combination thereof. Therefore, a dielectric layer of claim 1 reads upon a lamination part of Echigo that includes both the resin material disclosed by Echigo in one or more layers and the oxide disclosed by Savastiouk ‘170 in one or more of its layers. A preponderance of the evidence supports the Examiner’s determination that claim 1 would have been obvious over the combination of Echigo in view of Savastiouk ‘170. Appellants do not argue claims 26 and 28 separately from claim 1 (Appeal Br. 11—13). Accordingly, we affirm the Examiner’s rejection of claims 1, 26, and 28. Rejection over Echigo, Savastiouk ‘170, and Higashi Claims 2, 3, and 17—20 are rejected under 35 U.S.C. § 103(a) over the combination of Echigo, Savastiouk ‘170, and Higashi. No arguments regarding the propriety of the rejection have been submitted by Appellants (id. at 11—16). Therefore, we summarily affirm the § 103 rejection over Echigo, Savastiouk ‘170, and Higashi. Rejection over Higashi and Savastiouk ‘641 Claims 21—25 are rejected under 35 U.S.C. § 103(a) as obvious over the combination of Higashi in view of Savastiouk ‘641. The Examiner finds Higashi does not disclose or suggest, among other things, that first and second surfaces of the interposer substrate of Higashi are free from conductive material formed directly thereon, as recited in 7 Appeal 2017-001450 Application 12/774,558 independent claim 21 (Final Act. 8—9). Claims 22—25 depend from claim 21. The Examiner finds Savastiouk ‘641 discloses an integrated circuit structure in which the substrate of an interposer is free from conductive material formed directly thereon, citing Figures 2 and 11 of Savastiouk ‘641 (id. at 9). The Examiner concludes it would have been obvious to modify Higashi in view of Savastiouk ‘641 to provide an interposer substrate free from conductive material to prevent an electrical short between different conductive lines of its structure (id. ). Appellants contend the Examiner has not set forth a rationale with some rational underpinning to support the Examiner’s conclusion of obviousness (Appeal Br. 16). Appellants’ arguments are persuasive. In response to Appellants’ arguments, the Examiner states that the interposer substrate 140 depicted in Figure 11 of Savastiouk ‘641 can be made of silicon, which can be conductive, so the substrate 140 is free from conductive material (Ans. 6). The Examiner appears to refer to the intervening dielectric/oxide layer 410 and/or underfill 940 depicted in Figure 11 of Savastiouk ‘641 when stating the surfaces of substrate 140 are free from conductive material, such as metal contact pads 136C and copper vias 430.2 (Savastiouk ‘641 9:16-18; 10:48-50). It is unclear whether the Examiner concludes it would have been obvious to replace the interposer substrate 20 of Higashi and its electrical contact structure with the silicon substrate and electrical contact structure of Savastiouk ‘641 or to use the dielectric/oxide layer 410 and/or underfill 940 of Savastiouk ‘641 in the electrical contact structure of Higashi. Regardless of which modification, the Examiner’s rationale does not include articulated 8 Appeal 2017-001450 Application 12/774,558 reasoning with some rational underpinning to adequately explain why one of ordinary skill in the art would have undertaken such a modification in view of the disclosures of Savastiouk ‘641 and Higashi, which provides a resin substrate5 with functional electrical contacts. Instead, it appears the Examiner has engaged in impermissible hindsight when rejecting claim 21 over Higashi and Savastiouk ‘641. A fact finder must be aware “of the distortion caused by hindsight bias and must be cautious of arguments reliant upon ex post reasoning.” KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007) (citing Graham v. John Deere Co., 383 U.S. 1, 36 (1966) (warning against a “temptation to read into the prior art the teachings of the invention in issue”)). Furthermore, Appellants’ argument that Higashi does not disclose an interposer substantially free from integrated circuit devices, as recited in claim 21, is also persuasive. In view of the description in Appellants’ Specification at paragraph 16, Appellants’ drawings (which depict interposer layers lacking any integrated circuit device structures), Appellants’ arguments on appeal, and in view of the only guidance in Appellants’ disclosure for the scope or degree of “substantially” is from the drawings that there are no integrated circuit devices, we interpret “an interposer substantially free from integrated circuit devices” to mean that virtually no substantive parts of any integrated circuit devices are present in the interposer. The Examiner responds to Appellants’ argument by finding the substrate 20 and the insulating layer 32a beneath the substrate 20 of Higashi, 5 Higashi 128. 9 Appeal 2017-001450 Application 12/774,558 as well as the conductive materials of the insulating layer 32a, function as an interposer (Ans. 4). This finding, however, ignores the recitations of claim 21 that the interposer includes not only a first interconnect structure comprising a first dielectric layer overlying a first side of a substrate but also a second interconnect structure comprising a second dielectric layer overlying a second side of the substrate. The Examiner’s finding provides an interconnect structure and dielectric layer on only one side of a substrate. In the rejection, the Examiner finds dielectric layers 32a,b of Higashi function as the first and second dielectric layers for the first and second interconnect structures that overlie first and second sides of an interposer substrate, as recited in claim 21 (Final Act. 8). This finding may provide dielectric layers and interconnect structures that overlie first and second sides of a substrate (i.e., substrate 20) but each of the dielectric layers 32a,b on the top side of the substrate include devices (i.e., semiconductor chips 12), as depicted in Figure 3C of Higashi. Therefore, the disclosure of Higashi does not support the Examiner’s finding that Higashi discloses “an interposer substantially free from integrated circuit devices,” as recited in claim 21. For the above reasons, we do not sustain the Examiner’s § 103 rejection of claims 21—25 over Higashi and Savastiouk ‘641. DECISION On the record before us, we: A. sustain the Examiner’s decision to reject claims 1, 26, and 28 under 35 U.S.C. § 103(a) as being unpatentable over Echigo in view of Savastiouk ‘170; 10 Appeal 2017-001450 Application 12/774,558 B. sustain the Examiner’s decision to reject claims 2, 3, and 17—20 under 35 U.S.C. § 103(a) as being unpatentable over Echigo and Savastiouk ‘170 and further in view of Higashi; and C. do not sustain the Examiner’s decision to reject claims 21—25 under 35 U.S.C. § 103(a) as being unpatentable over Higashi in view Savastiouk ‘641. We affirm-in-part the decision of the Examiner to reject the claims. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1). AFFIRMED-IN-PART 11