Ex Parte Ford et al

Patent Trial and Appeal Board

Aug 16, 2017

12737476 (P.T.A.B. Aug. 16, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/737,476 03/22/2011 Simon Andrew Ford SCS-550-1343 4256
73459 7590 08/18/2017
NIXON & VANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203
EXAMINER
LINDLOF, JOHN M
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
08/18/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon @ firsttofile. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SIMON ANDREW FORD and STEPHEN JOHN
HILL
Appeal 2017-004966
Application 12/737,476
Technology Center 2100
Before ERIC B. CHEN, JEREMY J. CURCURI, and
AMBER L. HAGY, Administrative Patent Judges.
CURCURI, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 27—34. Final Act. 1. Claims 1—26 have been cancelled.
We have jurisdiction under 35 U.S.C. § 6(b).
Claims 27—34 are rejected under 35 U.S.C. § 103(a) as obvious over
Newbum (US 2005/0273310 Al; Dec. 8, 2005) and Christie (US 7,130,951
Bl; Oct. 31, 2006). Final Act. 2—8.
We reverse.
Appeal 2017-004966
Application 12/737,476
STATEMENT OF THE CASE
Appellants’ invention relates to “improving the performance of data
processors within multi processor or multi threaded systems.” Spec. 1:5—6.
Claim 27 is illustrative and reproduced below:
27. A processor for executing a data processing process, said
processor comprising:
an interface configured to provide a tuning process external to
said processor with observational access to at least some of a state of
said processor during execution of said data processing process and
output access to output tuning data relating to parameters of
speculative mechanisms of said processor,
wherein, through said interface, said tuning process accesses
observational data relating to at least some of the state of said
processor and tunes said parameters of speculative mechanisms of
said processor, so that said mechanisms speculate differently and
thereby improve a performance of said processor,
wherein a critical state of said processor is unaltered by said
tuning of said parameters, said critical state being a state whose
alteration causes a program executing on said processor to produce an
incorrect result.
ANALYSIS
The Examiner finds Newbum and Christie teach all limitations of
claim 27. Final Act. 2—3. The Examiner finds Newbum teaches (claim 27)
“an interface configured to provide a tuning process external to said
processor with observational access to at least some of a state of said
processor during execution of said data processing process and output access
to output tuning data relating to parameters of speculative mechanisms of
said processor.” Final Act. 2—3 (citing Newbum || 77—91). The Examiner
finds Christie teaches (claim 27) “wherein a critical state of said processor is
unaltered by said tuning of said parameters, said critical state being a state
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whose alteration causes a program executing on said processor to produce an
incorrect result.” Final Act. 3 (citing Christie col. 4,11. 9—25). The
Examiner reasons:
At the time of the invention it would have been obvious to
one of ordinary skill in the art to combine the teachings of
Newbum and Christie such that a critical state of said processor
is unaltered by said tuning of said parameters, said critical state
being a state whose alteration causes a program executing on said
processor to produce an incorrect result. This would have
enhanced the security of the environment to prevent malicious
software access.
Final Act. 3.
Among other arguments, Appellants present the following principal
arguments:
i. Newbum’s tuning process is internal to the processor. See App.
Br. 9—10 (“the module 215 that performs the tuning is inside the processor
205. The same is tme for modules 415 and 510 in respective processors 405
and 505. Newbum teaches an internal tuning process, and therefore, lacks
an external tuning process.”); see also App. Br. 11 (“By providing the tuning
process on an external processor separate from the main processor, the
processing power for the tuning process is not taken from the main
processor, and thus, does not adversely affect the operation of the main
processor.”); see also Reply Br. 2—3.
ii.
Because Newbum’s system relies on monitoring the activity of a
processor in order to provide a tuning process with information
necessary to tune the behavior of the processor, it would access
Christie’s secure/private data. But from Christie’s objectives,
that access is undesirable. On the other hand, if Newbum’s
system were denied information relating to the activity of the
processor when the processor processes secure/private data,
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Newbum’s objective of performance monitoring and tuning for
the overall system is undermined.
App. Br. 14; see also Reply Br. 7 (“Christie does not teach a way for the
instructions executed by a processor to be protected so that secure/protected
data cannot be accessed. Christie only describes protecting main memory.”)
and Reply Br. 8 (“The teaching of one reference eradicates the benefit of the
other reference because Christie requires obscurity for security/privacy and
Newbum requires transparency for monitoring and tuning. The Answer’s
construct of ‘partial access and tuning’ on page 3 contradicts Newbum’s
tuning approach that requires full monitoring access to the processor.”).
In response, the Examiner explains: “Newbum does recognize and
teach tuning processes external to a processor such as element 415 of figure
4, which is depicted as being external to the processor 405.” Ans. 2.
In response, the Examiner further explains:
Simply because certain areas are secured and protected
from monitoring or tuning does not mean that other areas
couldn’t be tuned. Christie teaches that a specific region of
memory is prevented from being accessed, not that all access
must be prevented. Newbum would certainly still be satisfactory
for its intended purpose of instmction processing and monitoring
even if some areas had limited access.
Ans. 3.
We review the appealed rejections for error based upon the issues
identified by Appellants, and in light of the arguments and evidence
produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential).
Appellants’ arguments persuade us that the Examiner erred in finding
Newbum teaches (claim 27) “an interface configured to provide a tuning
process external to said processor with observational access to at least some
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Application 12/737,476
of a state of said processor during execution of said data processing process
and output access to output tuning data relating to parameters of speculative
mechanisms of said processor.” Appellants’ arguments also persuade us that
the Examiner erred in the conclusion of obviousness because the Examiner’s
reasoning lacks a sufficient rational underpinning.
Regarding Appellants’ argument (i), we agree with Appellants that
claim 27’s language requires (claim 27 (emphasis added)) “a tuning process
external to said processor” and that, in Newbum, modules 215, 415, and 510
are inside processors 205, 405, and 505, respectively. See Newbum
Figures 2 and 3 (module 215), Figure 4 (module 415), Figure 5
(module 510), 1177-91.
Newbum (177) discloses: “module 215 in processor 205 is illustrated.
Module 215 is to tune a microarchitectural feature.” Newbum (1 88)
discloses: “module 410 and module 415 may have blurred boundaries, as
their functionality, hardware, software, or combination of hardware and
software may overlap.” Blurred boundaries between module 410 and
module 415, as well as Figure 4 itself, suggest module 410 and module 415
are internal to the processor. Newbum (| 94) discloses: “Processor 505
includes module 510.” These disclosures in Newbum support Appellants’
contention that Newbum’s tuning processes are internal to the processor.
On the record before us, the Examiner has not established that
Newbum teaches or suggests tuning processes that are external to the
processor, as recited in claim 27.
Regarding Appellants’ argument (ii), in making the rejection, the
Examiner reasons one of ordinary skill in the art would have been motivated
to combine the teachings of the references because “[t]his would have
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enhanced the security of the environment to prevent malicious software
access.” Final Act. 3. Christie (col. 4,11. 9—25) discloses creating a
protected memory region. That said, Newbum’s internal tuning module
requires the ability to monitor performance of microarchitectural features.
See Newbum || 77—91. Accordingly, the Examiner’s stated motivation of
preventing access is contrary to Newbum’s teachings, which require access
by Newbum’s internal tuning module. To the extent these differences
would have been reconciled (see Ans. 3), on the record before us, the
Examiner has not established that such a reconciliation is suggested by
Newbum and Christie, particularly in light of our analysis above where we
find the Examiner has not established that Newbum teaches or suggests
tuning processes that are external to the processor, as recited in claim 27.
For these reasons, on the record before us, the Examiner has erred in
the conclusion of obviousness because the Examiner’s reasoning lacks a
sufficient rational underpinning to support the conclusion of obviousness.
We, therefore, do not sustain the Examiner’s rejection of claim 27, or
of claims 28 and 29, which depend from claim 27.
Independent claim 30 recites “an interface configured to provide a
tuning process external to said processor with observational access to at least
some of a state of said processor during execution of said data processing
process and output access to output tuning data relating to parameters of
speculative mechanisms of said processor.” We, therefore, also do not
sustain the Examiner’s rejection of claim 30, or of claims 31—33, which
depend from claim 30.
Independent claim 34 recites “an interface configured to provide a
tuning process external to said processor with observational access to at least
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some of a state of said processor during execution of said data processing
process and output access to output tuning data relating to parameters of
speculative mechanisms of said processor.” We, therefore, also do not
sustain the Examiner’s rejection of claim 34.
ORDER
The Examiner’s decision rejecting claims 27—34 is reversed.
REVERSED
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