Ex Parte Dreps et al

Patent Trial and Appeal Board

Apr 13, 2016

12028953 (P.T.A.B. Apr. 13, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/028,953 02/1112008
126453 7590 04/15/2016
International Business Machines Corporation - IT
Rich Lau - IPLaw Department
2455 South Road, B/008-2
Poughkeepsie, NY 12601
Daniel M. Dreps
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
POU920070251US1 7827
EXAMINER
HENNING, MATTHEW T
ART UNIT PAPER NUMBER
2491
NOTIFICATION DATE DELIVERY MODE
04/15/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
poiplaw2@us.ibm.com
ituchman@tuchmanlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DANIEL M. DREPS, FRANK D. FERRALOLO,
ROBERT J. REESE, and MARTIN L. SCHMATZ
Appeal2014-005131
Application 12/028,953
Technology Center 2400
Before DAVID M. KOHUT, LINZY T. McCARTNEY, and
MATTHEW J. McNEILL, Administrative Patent Judges.
McNEILL, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1-23, which are all the claims pending in this application.
We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm-in-part.
1 According to Appellants, the real party in interest is International Business
Machines Corporation. App. Br. 2.
Appeal 2014-005131
Application 12/028,953
STATEMENT OF THE CASE
Introduction
Appellants' present application relates to reducing power
consumption in a communications system by changing the bit frequency of a
logic unit. Spec. i-f 3. Claim 1 is illustrative of the invention and reads as
follows:
1. A communication system comprising:
a logic unit to receive raw data having a first bit frequency
for transmission by the communication system, and to combine
a scramble pattern with the raw data at a second bit frequency,
wherein the second bit frequency is different than the first bit
frequency; and
a transmitter to transmit the combined raw data and
scramble pattern; and
wherein said logic unit is configured to dynamically alter
the second bit frequency in accordance with power dissipation
requirements of the communication system.
The Examiner's Rejection
Claims 1-23 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Corrigan (WO 85/00259; Jan. 17, 1985), Den Besten (US 6,549,595
Bl; Apr. 15, 2003), and Borza (US 2004/0158752 Al; Aug. 12, 2004). See
Final Act. 7-11.
ANALYSIS
Claim 1
We have reviewed the Examiner's rejection in light of the evidence of
record and Appellants' contentions that the Examiner has erred. We
disagree with Appellants' conclusions as to independent claim 1 and
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Application 12/028,953
dependent claims 4, 5, and 7-9. With regard to claims 1, 4, 5, and 7-9, and
except as noted below, we adopt as our own: (1) the findings and reasons set
forth by the Examiner in the action from which this appeal is taken and (2)
the reasons set forth by the Examiner in the Examiner's Answer in response
to Appellants' Appeal Brief. We concur with the conclusions reached by the
Examiner for claims 1, 4, 5, and 7-9. We highlight the following additional
points.
Appellants argue the Examiner erred in finding Corrigan, Den Besten,
and Borza teach or suggest "said logic unit is configured to dynamically
alter the second bit frequency in accordance with power dissipation
requirements of the communication system." See App. Br. 4-8. In
particular, Appellants argue neither Corrigan nor Den Besten teaches or
suggests a bit frequency at which a scramble pattern is combined with raw
data. App. Br. 8. Appellants argue Borza does not teach or suggest
combining a scramble pattern with raw data, instead disclosing va1ying the
clock frequency provided to functional circuit blocks to conserve power.
App. Br. 6. Appellants argue changing the clock rate or clock frequency is
not the same as changing the bit frequency because two circuits may operate
at different clock frequencies but still have the same bit frequency. App. Br.
6.
As found by the Examiner, Corrigan and Den Besten teach encryption
circuitry which combines a scramble pattern with raw data. Ans. 3. The
proposed combination would add Borza's teaching that reducing the clock
rate for a circuit (such as the scrambler), allows for the dynamic reduction of
power consumption. Id. Appellants' argument that Borza does not teach
combining a scramble pattern with raw data focuses on the disclosure of
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Application 12/028,953
Borza while ignoring the disclosures of Corrigan and Den Besten. One
cannot show nonobviousness by attacking references individually when the
rejection is based on a combination of references. In re Merck & Co. Inc.,
800 F.2d 1091, 1097 (Fed. Cir. 1986); see also In re Keller, 642 F.2d 413,
425 (CCPA 1981 ). The Examiner explained that the combination of
Corrigan, Den Besten, and Borza, not Borza alone, discloses this limitation.
Ans. 3. Accordingly, Appellants have not persuaded us the Examiner erred
in rejecting claim 1 over the cited combination.
Appellants' argument that Borza does not teach dynamically
modifying a "bit frequency" because it teaches modifying a "clock rate" or
"clock frequency" is also unpersuasive. As found by the Examiner, in the
proposed combination of references, reducing the clock frequency of the
scrambler will reduce the bit rate (or bit frequency). Ans. 4. Appellants'
argument is unpersuasive because Borza need not recite the exact claim
language because modifying the clock frequency also affects the bit
frequency. See Standard Havens Prods. v. Gencor Indus., 953 F.2d 1360,
13 69 (Fed. Cir. 1991) (a prior art reference "need not duplicate word for
word what is in the claims."). Further, this is consistent with the teachings
of Appellants' Specification, which does not explicitly recite modifying the
"bit frequency" to reduce power consumption, instead disclosing modifying
the frequency based on the clock rate. See Spec. i-f 51.
Appellants further argue the Examiner erred in rejecting claim 1
because the Examiner applied impermissible hindsight, arguing that "the
Office takes the position that claim 1 is obvious because Borza teaches that a
clock frequency can be adjusted somewhere in a circuit in response to power
requirements." Reply Br. 3 (citing Ans. 3). We disagree with Appellants.
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Application 12/028,953
The Examiner's proposed combination would apply Borza's power
reduction teachings to the encryption circuitry taught by Corrigan and Den
Besten. Ans. 3--4. As acknowledged by Appellants, Borza's teachings are
not limited to a particular type of functional circuit. See App. Br. 6.
Appellants further acknowledge that Borza teaches reducing the clock
frequency, and therefore power consumption, in an encryption block of a
circuit. See id. The Examiner's proposed combination is similar, with the
encryption circuitry taught by Corrigan and Den Besten taking the place of
the encryption block taught in Borza. See Ans. 3. Although the Supreme
Court stated that "[a] factfinder should be aware, of course, of the distortion
caused by hindsight bias and must be cautious of arguments reliant upon ex
post reasoning" (KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007)),
we are satisfied that the combination of Corrigan, Den Besten, and Borza is
not based on hindsight bias. In fact, the proposed combination involves
nothing other than requiring the ordinarily skilled artisan to use common
sense in combining prior art elements that perform their ordinary functions
to predictably result in the claimed system.
Claims 2, 3, 11, and 12
With regard to claims 2, 3, 11, and 12, we agree with Appellants that
the Examiner erred. Claim 2 recites, "[ t] he system of claim 1 further
comprising a control register to limit the combining of the scramble pattern
performed by said logic unit." Claim 11 recites a similar limitations.
Claims 3 and 12 depend from claims 2 and 11, respectively.
Appellants argue the Examiner erred in rejecting claim 2 because the
Examiner's rejection is based on "unsubstantiated allegations devoid of fact
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Application 12/028,953
finding." Appeal Br. 8-9. The Examiner responds that claim 2 does not
require that the control register limit the pattern to the particular bits output
at particular moments when the register is clocked. Ans. 6. The Examiner
finds Corrigan teaches the scramble pattern is stored in the k-bit shift
register 26, which outputs particular bits of the register to be combined and
used to scramble the plaintext data at element 25. Id. The Examiner finds
this meets the "control register" limitation of claim 2.
Appellants agree with the Examiner's interpretation of Corrigan, in
part. See Reply Br. 4-5. Appellants agree that claim 2 does not require
limiting the pattern to particular bits output at the moment the register is
clocked. Reply Br. 4. Appellants further agree that the particular bits of
Corrigan that are used to scramble the plaintext data correspond to the
claimed "scramble pattern." Id. Appellants argue, however, that the
Examiner is interpreting the particular bits output by the control register as
both the scramble pattern recited in claim 1 and the limitation of the
scramble pattern recited in claim 2. Id. Appellants argue the particular bits
output by the control register cannot satisfy both claim elements and
Corrigan therefore does not teach or suggest claim 2. Id.
As found by the Examiner, Corrigan teaches a k-bit shift register that
outputs particular bits to be combined with raw data to scramble the raw
data. Ans. 6; Final Act. 9 (citing Corrigan 10:22-14: 19). Thus, the
particular bits output by the k-bit shift register correspond to the "scramble
pattern" that is combined with raw data to scramble that data. As a result,
Appellants have persuaded us that the Examiner has not established that
Corrigan teaches further limiting these particular bits with a control register
as required by claim 2. Accordingly, on the record before us and by a
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Application 12/028,953
preponderance of the evidence, we are constrained to reverse the Examiner's
rejection of claim 2. 2
CONCLUSIONS
On the record before us and in view of the analysis above, we are not
persuaded by Appellants' contentions that the Examiner erred in rejecting
claim 1. Therefore, we sustain the rejection of claim 1 under 35 U.S.C.
§ 103(a) as unpatentable over Corrigan, Den Besten, and Borza. Appellants
argue the patentability of independent claims 10 and 19 based on the same
reasons presented for claim 1. See App. Br. 8. We, therefore, sustain the
rejection of claims 10 and 19 under 35 U.S.C. § 103(a) as unpatentable over
Corrigan, Den Besten, and Borza for the same reasons as set forth above.
We also sustain the rejection of dependent claims 6, 15, and 20-23 under 35
U.S.C. § 103(a) as unpatentable over Corrigan, Den Besten, and Borza
because these claims were not argued separately. See App. Br. 8-15.
On the record before us and in view of the analysis above, we are not
persuaded by Appellants' contentions that the Examiner erred in rejecting
claims 4, 5, or 7-9. Therefore, we sustain the rejection of claims 4, 5, and
7-9 under 35 U.S.C. § 103(a) as unpatentable over Corrigan, Den Besten,
and Borza. Appellants argue the patentability of claims 13, 14, and 16-18
based on the same reasons presented for claims 4, 5, and 7-9. See App. Br.
15. We, therefore, sustain the rejection of claims 13, 14, and 16-18 under
2 Because we are persuaded of error with regard to the identified issue,
which is dispositive of the rejections of claims 2, 3, 11, and 12, we do not
reach the additional issues raised by Appellants' arguments.
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Application 12/028,953
35 U.S.C. § 103(a) as unpatentable over Corrigan, Den Besten, and Borza
for the same reasons as set forth above.
On the record before us and in view of the analysis above, we are
persuaded by Appellants' contentions that the Examiner erred in rejecting
claim 2. Therefore, we do not sustain the rejection of claim 2, claim 11
which recites similar limitations, and claims 3 and 12 dependent therefrom.
DECISION
We affirm the decision of the Examiner to reject claims 1, 4--10, and
13-23.
We reverse the decision of the Examiner to reject claims 2, 3, 11, and
12.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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