Ex Parte Dennen

Patent Trial and Appeal Board

Apr 27, 2016

13269814 (P.T.A.B. Apr. 27, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/269,814
96051 7590
Uniloc USA Inc.
Legacy Town Center
7160 Dallas Parkway
Suite 380
Plano, TX 75024
10/10/2011
04/29/2016
FIRST NAMED INVENTOR
Michael W. Dennen
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
UN-NP-FT-117 9236
EXAMINER
PIZARRO CRESPO, MARCOS D
ART UNIT PAPER NUMBER
2814
NOTIFICATION DATE DELIVERY MODE
04/29/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
sean. burdick@unilocusa.com
tkiatkulpiboone@unilocusa.com
kris.pangan@unilocusa.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL W. DENNEN
Appeal2014-001590
Application 13/269,814
Technology Center 2800
Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF CASE
Appellant2 appeals the Examiner's decision to reject claims 1, 3-11,
and 13-20 under 35 U.S.C. § 103(a). Claims 1, 3, 6, 9-11, 13, 14, and 17-
1 In our opinion below, we refer to the Specification filed October 10, 2011
(Spec.), Final Office Action mailed January 30, 2013 (Final), the Appeal
Brief filed July 6, 2013 (Appeal Br.), and the Examiner's Answer mailed
September 10, 2013 (Ans.).
2 Appellant identifies the real party in interest as Uniloc USA, Inc. and
Uniloc Luxembourg S.A. Appeal Br. 3.
Appeal2014-001590
Application 13/269,814
20 stand rejected as obvious over Colombo3 in view ofMilligan. 4 To reject
claims 4, 5, 7, 8, 15, and 16, the Examiner adds Hillman. 5 We have
jurisdiction under 35 U.S.C. §§ 6(b) and 134(a).
We AFFIRM.
The claims are directed to methods of fabricating a field effect
transistor gate including a metal nitride layer (see, e.g., claims 1, 13, and 19)
and devices so fabricated (see, e.g., claims 11 and 18). According to the
Specification, this type of gate was known in the art, and prior work has
been devoted to producing a metal nitride gate over Si02 or Partially
Nitrided Oxide (PNO). Spec. 1-2. Appellant states that the structure
proposed in the literature "does not appear to have been realized with high
reliability, low trapped charge and/or low dielectric leakage." Spec. 3 i-f 1.
Appellant's method includes one or two steps of annealing performed at
specific points in the method of forming the gate, which Appellant states
reduce or eliminate the prior difficulties. Id. Appellant's claims are directed
to the method including the annealing steps (see, e.g., claim 1 (two
annealing steps) and claim 13 (one annealing step), or a step of reducing
interaction between the gate insulating layer and the metal nitride layer (see,
e.g., claim 19). 6 Claim 1 is illustrative of the two-step annealing method:
1. A method of fabricating an integrated circuit field
effect transistor gate, the method comprising:
3 US 7,091,119 B2, issued August 15, 2006.
4 US 7,713,874 B2, issued May 11, 2010.
5 US 5,975,912, issued November 2, 1999.
6 According to the Specification, both annealing steps reduce the interaction
between the gate insulating layer (Si02 or PNO) and the metal nitride layer.
Spec. 3--4. Thus, the reducing step encompasses either step of annealing.
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Appeal2014-001590
Application 13/269,814
fabricating a gate insulating layer on an integrated circuit
substrate;
fabricating a metal nitride layer on the gate insulating
layer;
annealing the metal nitride layer in a first nitridizing
ambient;
fabricating a cap on the metal nitride layer that has been
annealed in the nitridizing ambient;
etching the cap and the metal nitride layer that has been
annealed in the first nitridizing ambient to expose sidewalls
thereof; and
annealing a sidewall of the metal nitride layer in a
second nitridizing ambient.
Claims Appendix, Appeal Br. 18 (emphasis added).
Appellant does not argue any claim apart from the others, nor the
secondary rejection apart from the primary rejection. Appeal Br. 13-17.
However, the issues raised are different for each independent claim. Thus,
we consider the issues as they relate to the rejection of claims 1, 13, and 19.
OPINION
Claim 1
Claim 1 requires both annealing steps. The first annealing step
involves annealing the metal nitride layer formed on the gate insulating layer
in a first nitridizing ambient. The second annealing step occurs after an
etching step that exposes a metal nitride sidewall. The second annealing
step anneals the sidewall in a second nitridizing ambient. The nitridizing
ambient may be, ammonia (NH3) or other nitiriding gases. Spec. 3--4.
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Appeal2014-001590
Application 13/269,814
The Examiner finds that Colombo teaches a method of forming a
transistor gate including a metal nitride layer (TiN) that includes a step of
annealing a sidewall of the TiN layer in a nitridizing ambient (the second
annealing step of claim 1 ), but acknowledges that Colombo does not teach
annealing the TiN in a first nitridizing ambient (the first annealing step of
claim 1). Final 2-3. However, the Examiner concludes that including the
first annealing step would have been obvious to the ordinary artisan based
upon the teachings of Milligan. Final 3.
Appellant contends that Colombo teaches against annealing because
Colombo seeks to overcome a poly-silicon depletion problem by
encapsulating the transistor gate with silicon nitride, which Appellant alleges
promotes interaction between the poly-silicon layer and encapsulating
nitride layer; an effect opposite from Appellant's annealing step. Appeal Br.
13-15. Appellant further contends that annealing Colombo's gate structure
according to Milligan would render Colombo's structure unsuited for its
intended purpose for a similar reason: Annealing would prevent interaction
between the nitride sidewalls and the poly-silicon layer and cause poly-
silicon depletion. Appeal Br. 16.
For claim 1, Appellant's arguments are not persuasive for the reasons
the Examiner provides in the Answer. Ans. 5-6. As found by the Examiner,
Colombo discloses forming a TiN layer 312 by a deposition process 314, but
Colombo does not provide any details of the deposition process. Ans. 5-6;
Colombo, col. 6, 11. 57-62; Colombo, Fig. 5B. Milligan teaches a method of
depositing a metal nitride layer by atomic layer deposition (ALD). Milligan,
col. 1, 11. 7-10; col. 9, 1. 20-col. 13, 1. 8. Because Colombo does not provide
the details of metal nitride deposition and Milligan discloses a suitable
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Appeal2014-001590
Application 13/269,814
method, the evidence supports the Examiner's finding of a reason to use
Milligan's deposition method.
Milligan's ALD method includes a plasma annealing process in a
nitridizing ambient. Milligan, col. 1, 11. 7-1 O; see also, e.g. col. 10, 11. 16-
17. One of the benefits of the plasma annealing process, according to
Milligan, is to enable a controlled and conformal deposition of the metal
nitride film. Milligan, col. 4, 11. 9-12. Thus, the evidence supports the
Examiner's reason for combining the film deposition teachings of Milligan
with the method of forming a gate having a TiN layer as taught by Colombo.
Moreover, we find no disclosure in Colombo or other evidence of
record supporting Appellant's argument that annealing would eliminate a
desired interaction between the poly-silicon layer and metal nitride layer of
Colombo's gate. In fact, Colombo's silicon nitride encapsulation layer 120
and nitride materials 126 (see Colombo, Fig. 3) serve to condition or repair
the sidewalls that are damaged during etching (e.g., the encapsulation layers
renitride the metal nitride layer damaged by etching), and protects against
oxidation of the sidewall metal. Colombo, col. 5, 11. 28-38. Like Appellant,
Colombo seeks to protect the metal nitride layer from loss of nitride and
from oxidation. Compare Colombo, col. 5, 11. 28-3 8 with Spec. 3--4.
Moreover, the Examiner has provided an unrebutted reason for making the
combination ("to enable controlled and conformal deposition of the TiN thin
films") that is supported by the evidence of record (Milligan, col. 4, 11. 8-
41 ). Final3.
Claim 13
Claim 13 does not require the first annealing step recited in claim 1; it
only includes the second annealing step, i.e., annealing the sidewall. The
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Appeal2014-001590
Application 13/269,814
Examiner finds that Colombo teaches the sidewall annealing step (second
annealing step). Ans. 5. Thus, Appellant's arguments do not identify a
reversible error in the Examiner's rejection of claim 13.
Claim 19
Claim 19 contains no explicit annealing steps, but recites "reducing
interaction between the gate insulating layer and the metal nitride layer."
Appellant's Specification discloses that annealing the sidewall reduces the
claimed interaction. Spec. 3--4. Because Appellant has not identified a
reversible error in the Examiner's finding that Colombo discloses annealing
the sidewall, Appellant has not identified a reversible error in the
Examiner's rejection of claim 19.
CONCLUSION
We sustain the Examiner's rejections.
DECISION
The Examiner's decision is affirmed.
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l ).
AFFIRMED
6