Ex Parte Circello et al

Patent Trial and Appeal Board

Aug 30, 2017

13283187 (P.T.A.B. Aug. 30, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/283,187 10/27/2011 Joseph C. Circello AC50271HH-US01 1067
23125 7590 09/01/2017
NXP USA, Inc.
LAW DEPARTMENT
6501 William Cannon Drive West TX30/OE62
AUSTIN, TX 78735
EXAMINER
LOONAN, ERIC T
ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
09/01/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip. department .u s @ nxp. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JOSEPH C. CIRCELLO and JAMES ANDREW
COLLIER A. SCOBIE1
Appeal 2017-005647
Application 13/283,187
Technology Center 2100
Before ERIC B. CHEN, JEREMY J. CURCURI, and
MICHAEL M. BARRY, Administrative Patent Judges.
CURCURI, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1—8 and 10—20. Final Act. 1. Claim 9 has been
cancelled. We have jurisdiction under 35 U.S.C. § 6(b).
Claims 1—6, 8, 10, 11, and 13—20 are rejected under 35 U.S.C.
§ 102(b) as anticipated by McKee (US 2003/0115476 Al; June 19, 2003).
Final Act. 2—16.
Claims 7 and 12 are rejected under 35 U.S.C. § 103(a) as obvious over
McKee and Conti (US 2007/0011419 Al; Jan. 11, 2007). Final Act. 17-20.
We affirm.
1 According to Appellants, the real party in interest is Freescale
Semiconductor, Inc. See Appeal Br. 2
Appeal 2017-005647
Application 13/283,187
STATEMENT OF THE CASE
Appellants’ invention relates to “controlling access to shared system
resources.” Spec. 11. Claim 1 is illustrative:
1. An electronic system comprising:
multiple data access components, each configured to
issue access requests, which request access to a shared system
resource, where a region descriptor is associated with the shared
system resource, and wherein the region descriptor specifies,
for the shared system resource, default access permissions for
the multiple data access components;
a semaphores module configured to implement a
semaphore for the shared system resource, and to produce
semaphore signals indicating which one, if any, of the multiple
data access components has locked the semaphore for the
shared system resource;
a memory protection unit configured to receive the
semaphore signals on hardware connections between the
semaphore module and the memory protection unit, wherein the
memory protection unit includes effective permissions logic
that determines effective access permissions from the default
access permissions and the semaphore signals, and the memory
protection unit is further configured to grant or deny the access
requests based on the effective access permissions, wherein the
effective access permissions produced by the memory
protection unit for a first data access component are different
from the default access permissions for the first data component
when the semaphore signals indicate that a second data access
component has locked the semaphore for the shared system
resource;
a system interconnect through which the access requests
are communicated from the multiple data access components to
the memory protection unit; and
the hardware connections between the semaphores
module and the memory protection unit, wherein the hardware
connections are distinct from the system interconnect, and the
semaphore signals are communicated between the semaphores
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Appeal 2017-005647
Application 13/283,187
module and the memory protection unit through the hardware
connections.
PRINCIPLES OF LAW
We review the appealed rejections for error based upon the issues
identified by Appellants, and in light of the arguments and evidence
produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential).
ANALYSIS
The Anticipation Rejection of Claims 1-6, 8,10,11, and 13-20 by
McKee
The Examiner finds McKee describes all limitations of claim 1. Final
Act. 2—5.
Appellants present the following principal arguments:
McKee clearly fails to disclose a system in which
specific logic (e.g., “effective access permissions logic”) is used
to produce effective access permissions based on default access
permissions and semaphore signals that are received over
hardware connections that are distinct from a system
interconnect (e.g., a bus), and where the effective access
permissions are different from the default access permissions
under certain circumstances.
App. Br. 16; see also App. Br. 17—18.
We do not see any error in the contested findings of the Examiner.
The Examiner finds McKee teaches the recited memory protection
unit. Final Act. 3^4 (citing McKee H 31, 33, Abstract); see also Ans. 5—6
(citing McKee H 31, 33, 38, 81). We agree with and adopt these findings as
our own.
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Application 13/283,187
McKee (Figure 6,131) discloses access rights encoding used in a
translation look-aside buffer (TLB) entry (standard READ, WRITE, and
EXECUTE access rights associated with privileged levels).
McKee (133 (emphasis added)) discloses:
In one embodiment of the present invention, the
protection-key mechanism, discussed above, is used in
conjunction with standard semaphore techniques in order to
provide hardware-enforced semaphores to processes and
threads that allow the processes and threads to serialize or
partially serialize their accesses to memory. The protection-key
mechanism, as discussed above, provides a hardware-level
memory access control in addition to standard READ, WRITE,
and EXECUTE access right associated with privileged levels,
as described with reference to FIG. 6. One of a pool of
protection keys can be assigned, by a privilege-level-0 kernel
routine, to each memory region protected by a semaphore.
Semaphore routines call kernel routines to insert the protection
key into a protection-key register for a process or thread that
obtains access to the memory by calling semaphore routines, as
well as into an internal data structure associated with the
process or thread, and to remove the protection key from the
protection-key register via a kernel-routine call, as well as from
the internal data structures, when the process or thread calls a
semaphore routine to relinquish access to the memory region.
McKee (138) discloses:
The constant “SEMKEY,” declared on line 14, identifies
a particular protection-key register into which a semaphore-
related protection key is inserted during acquisition, by a
processor or thread, of a grant to access a memory region via a
semaphore routine. In the current implementation, the
protection key associated with the memory protected by a
semaphore is always inserted into one particular protection-key
register as well as into a table included within, or referenced
from, a process control block for the process or thread.
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Appeal 2017-005647
Application 13/283,187
Thus, McKee discloses the functionality of the recited memory
protection unit. In particular, McKee discloses determining effective access
permissions (McKee’s hardware-level memory access control in addition to
standard READ, WRITE, and EXECUTE access right associated with
privileged levels) from the default access permissions (McKee’s TLB entry
includes standard READ, WRITE, and EXECUTE access right associated
with privileged levels) and the semaphore signals (McKee’s semaphores
include hardware-level memory access control). The effective access
permissions may differ from the default access permissions in McKee when,
for example, the accessing process lacks the proper protection key (because
a second process has locked the semaphore). See McKee H 31, 33, and 38.
The Examiner also finds McKee teaches the recited hardware
connections between the semaphore module and memory protection unit
being distinct from the system interconnect through which the access
requests are communicated from the multiple data access components to the
memory protection unit. Final Act. 4—5 (citing McKee 118, Fig. 1); see also
Ans. 3—5. In particular, the Examiner finds that by teaching “the
interconnect between Processor 108 (analogous to the memory protection
unit) and registers 130 (analogous to the semaphores module) as a distinct
interconnect from internal busses 116/117 and interconnect device 120
(analogous to system interconnects), thus [McKee] teaches hardware
connections distinct from a system interconnect used to convey semaphore
signals.” Id. at 5. We agree with and adopt this finding as our own.
McKee (Figure 1,118) discloses the physical components of a
computer system including processor 108, memory 110, 112, and 114, buses
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Appeal 2017-005647
Application 13/283,187
and signal lines 116—119, interconnect devices 120, 122, and peripheral
interface cards 124—129.
Thus, McKee discloses the recited hardware connections between the
semaphore module and memory protection unit being distinct from the
system interconnect through which the access requests are communicated
from the multiple data access components to the memory protection unit. In
particular, McKee discloses a system interconnect (interconnect device 120)
through which access requests are communicated from multiple data access
components to the memory protection unit (processor 108), and distinct
hardware connections (inside processor 108) between the semaphore module
(registers 130) and the memory protection unit (processor 108). See McKee
118.
We, therefore, sustain the Examiner’s rejection of claim 1. We also
sustain the Examiner’s rejections of claims 2—6, 8, 10, 11, and 13—20, which
are not separately argued with particularity.
The Obviousness Rejection of Claims 7 and 12 over McKee and Conti
The Examiner finds McKee and Conti teach all limitations of claims 7
and 12. Final Act. 17—20.
Appellants argue: “Conti fails to make up for the deficiencies in
McKee.” App. Br. 18.
For reasons discussed above in addressing the anticipation rejection,
we find McKee is not deficient.
We, therefore, sustain the Examiner’s rejections of claims 7 and 12.
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Appeal 2017-005647
Application 13/283,187
ORDER
The Examiner’s decision rejecting claims 1—8 and 10—20 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED
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