Ex Parte Afriat

Patent Trial and Appeal Board

Apr 25, 2016

11964057 (P.T.A.B. Apr. 25, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
111964,057 12/26/2007
77215 7590 04/25/2016
MPG, LLP AND SANDISK
710 LAKEWAY DRIVE SUITE 200
SUNNYVALE, CA 94085
FIRST NAMED INVENTOR
Itshak Afriat
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SANDP046 1192
EXAMINER
PARIKH, KALPIT
ART UNIT PAPER NUMBER
2137
MAILDATE DELIVERY MODE
04/25/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ITSHAK AFRIAT
Appeal2014-005080
Application 11/964,057
Technology Center 2100
Before ALLEN R. MacDONALD, HUNG H. BUI, and
JOHN F. HORVATH, Administrative Patent Judges.
MacDONALD, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2014-005080
Application 11/964,057
STATEMENT OF CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 41--44, 46-54, 56-62, 64--72, and 74--76, which
constitute all the claims pending in this application. We have jurisdiction
under 35 U.S.C. § 6(b). 1
Exemplary Claim
Exemplary claim 41 under appeal reads as follows (emphasis added):
41. A storage device for servicing commands that use
logical addresses to reference memory contents, the storage
device comprising:
a flash memory; and
a controller configured to translate logical addresses in a
command to physical addresses using a mapping table that the
controller constructs in volatile memory during initialization of
the storage device based on data retrieved from the flash
memory,
wherein the controller is operative to,
service an access command, for initializing a host using
information programmed into firmware of the flash memory,
before the controller completes the construction of the mapping
table, the access command being serviced when a logical
address satisfying a predefined condition is within a predefined
range, the servicing of the access command is performed before
completion of the initialization of the storage device and the
servicing does not require building or referencing of the
mapping table and
1 Despite statements to the contrary (e.g., App. Br. 3; Ans. 3), claims 45, 55,
63, and 73, have been cancelled by Appellant's Amendment filed on May
29, 2013. These claims are not before the panel and are not discussed
further herein.
2
Appeal2014-005080
Application 11/964,057
disregard an access command, which does not include
logical address satisfying the predefined condition, if the
construction of the mapping table has not yet completed.
Rejection
The Examiner rejected claims 41--44, 46-54, 56-62, 64--72, and 74--
76 under 35 U.S.C. § 103(a) as being unpatentable over the combination of
Yamamoto et al. (US 2007/0067603 Al; Mar. 22, 2007) and Wilson et al.
(US 2001/0042166 Al; Nov. 15, 2001). 2
Appellant's Contentions3
1. Appellant contends that the Examiner erred in rejecting claim
41 under 35 U.S.C. § 103(a) because:
2 Separate patentability is not argued for claims 42--44, 46-54, 56-62, 64--
72, and 74--76. Except for our ultimate decision, this claim is not discussed
further herein.
3 In the Reply Brief, i\ppellant presents for the first time nev,r arguments
against the rejection of claim 41.
In the absence of a showing of good cause by Appellant, we decline to
consider an argument raised for the first time in the Reply Brief. This is
because, as the Examiner has not been provided a chance to respond, and in
the absence of a showing of good cause by Appellant, these arguments
would be deemed waived. See 37 C.F.R. § 41.4l(b)(2) (2012); In re Hyatt,
211F.3d1367, 1373 (Fed. Cir. 2000) (noting that an argument not first
raised in the brief to the Board is waived on appeal); Ex parte Nakashima,
93 USPQ2d 1834, 1837 (BP AI 2010) (informative) (explaining that
arguments and evidence not timely presented in the principal Brief, will not
be considered when filed in a Reply Brief, absent a showing of good cause
explaining why the argument could not have been presented in the Principal
Brief); Exparte Borden, 93 USPQ2d 1473, 1477 ( BPAI 2010) (informative)
("[p ]roperly interpreted, the Rules do not require the Board to take up a
belated argument that has not been addressed by the Examiner, absent a
showing of good cause."). Appellant has provided this record with no such
showing of good cause.
3
Appeal2014-005080
Application 11/964,057
The Examiner states that the information programmed in the
firmware constitutes a mapping table and that Yamamoto is
considered to disclose this feature because Yamamoto teaches a
program storage area with a mapping table that is equivalent to
the firmware. (See page 2 of the Advisory Action dated June
11, 2013). Appellant disagrees with this assertion. The address
translation table for the PSA includes mapping information for
each physical address in the PSA and the controller is used to
interpret the mapping of the logical address to identify the
corresponding physical address.
This is not the same as the information that is programmed
into the firmware of the instant application. The instant
application does not require construction (i.e., generation) of
any address translation table/mapping table or require the
controller, during initialization of a host, to interpret any
logical addresses to physical addresses using the address
translation/mapping table. Instead, as disclosed in the as-filed
Specification, the embodiments describe how the storage device
is configured to process the host device initialization request by
using the information programmed in the firmware so as to
respond within a shortened response time. (See page 9, fourth
full paragraph to page 11; third full paragraph).
App. Br. 8; Appellant emphasis omitted, Panel emphasis added.
2. Appellant contends that the Examiner erred in rejecting claim
41 under 35 U.S.C. § 103(a) because:
[T]he Office has failed to show Yamamoto teaching,
"access command being serviced by a controller when a logical
address satisfying a predefined condition is within a predefined
range ... ," (see page 3 of Final OA dated March 27, 2013). The
cited section in paragraphs [0122] and [0176] merely teach
availability of the PSA while the address translation table for
the DSA is being generated to access the DSA. Nowhere in the
cited sections or anywhere in Yamamoto is there an explicit
mention of a verification being made to determine if the
logical address satisfying a predefined condition falls within a
predefined range.
4
Appeal2014-005080
Application 11/964,057
App. Br. 8-9; Appellant emphasis omitted, Panel emphasis added.
3. Appellant contends that the Examiner erred in rejecting claim
41 under 35 U.S.C. § 103(a) because:
[A] portion (PSA) of the storage device is built by generating
address translation table for the PSA portion and access
provided while the building of the remaining DSA portion of
the storage area is continues, during initialization. This is not
the same as servicing a request for initialization of a host before
controller completes construction of the mapping table during
initialization of the storage device.
App. Br. 9.
4. Appellant contends that the Examiner erred in rejecting claim
41 under 35 U.S.C. § 103(a) because:
The teachings of Yamamoto are not directed toward servicing
access commands for initialization of a host device while the
storage device is initializing. Instead, the teachings of
Yamamoto are directed toward servicing a command for
accessing the memory device during initialization of the storage
device by allowing access to PSA portion using the address
translation table of the PSA while the address translation table
for DSA is being built.
Appellants would like to clarify the difference between
the "access commands" and "commands" as recited in the
claimed embodiments. The commands recited in the claimed
embodiment are external commands (either initiated by a host
device or by other device) to access different areas of the
memory of the storage device and such commands are serviced
after initialization of the storage device. The access commands,
on the other hand, are commands used to initialize a host.
App. Br. 9-10.
5
Appeal2014-005080
Application 11/964,057
5. Appellant contends that the Examiner erred in rejecting claim
41 under 35 U.S.C. § 103(a) because:
Wilson teaches generating a mapping table mapping the logical
address to physical address within the disk drive system in
order for the commands to be serviced. (See at least paragraph
[0019], reference numeral 40 of Figure 2, reference numeral
132, 136 of Figure 5). As a result, Wilson does not cure the
deficiencies of Yamamoto.
App. Br. 10.
Issue on Appeal
Did the Examiner err in rejecting claim 41 as being obvious for the
reasons argued by Appellant?
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellant's
arguments (Appeal Brief and Reply Brief) that the Examiner has erred. We
disagree with Appellant's conclusions. Except as noted below, we adopt as
our own (1) the findings and reasons set forth by the Examiner in the action
from which this appeal is taken and (2) the reasons set forth by the Examiner
in the Examiner's Answer in response to Appellant's Appeal Brief. We
concur with the conclusions reached by the Examiner. We highlight the
following additional points.
As to Appellant's above contentions 1 and 3, we disagree for the
reasons set forth by the Examiner. Ans. 24--26. Additionally, we note that
Yamamoto's PSA (program storage area) is read only and is addressable via
an address translation table that has been generated and stored in the table
block prior to initialization of the DSA (data storage area), and the DSA's
6
Appeal2014-005080
Application 11/964,057
address translation table. See Yamamoto ilil I 5, 24, 7 6. The PSA' s address
translation table maps logical addresses to physical addresses within the
PSA. Id. i-f 15. The PSA is used to store programs for both the memory
controller and the host device, including a boot program for the host device,
which can be read during initialization of the DSA, and creation of the
DSA's address translation table. Id. i-fi-176, 187-189.
Appellant's Specification describes a similar method to allow a host
computer to boot during memory device initialization. In particular, prior to
initialization, Appellant programs the memory device to store the host's boot
code at a logical address, and "to create and store an association of the
logical address with the physical address, wherein the storage device stores
the host boot code." Spec. 10: 10-16 (emphasis added). This association
between the boot code's logical address and the physical address in the
storage device where the boot code is stored is equivalent to Yamamoto' s
PSA address translation table. This is because Yamamoto's PSA address
translation table maps logical addresses to physical addresses within the
PSA, including physical addresses where host boot code is stored. See
Yamamoto i-fi-115, 76, 187-189. Thus, we agree with the Examiner's
conclusion that Appellant's claim encompasses use of Yamamoto' s PSA
mapping table before completion of the construction of the full (PSA+DSA)
address mapping table.
As to Appellant's above contention 2, we disagree for the reasons set
forth by the Examiner at page 25 of the Answer.
As to Appellant's above contention 4, we disagree for the reasons set
forth by the Examiner at pages 26-27 of the Answer. Additionally,
Appellant's Specification states:
7
Appeal2014-005080
Application 11/964,057
The controller can service a variety of access commands, such
as read commands, a write commands and erase commands.
Spec. 7:21-23, emphasis added. Our review of Appellant's Specification
does not find an "access command" to be limited in the manner now argued
by Appellant.
As to Appellant's above contention 5, we disagree because we do not
find Yamamoto to be deficient as argued by Appellant for the reasons
explained supra. Moreover, the Examiner cited Wilson for teaching
firmware is software programmed into a flash memory. See Final Act. 3;
Wilson i-fi-14, 33. Yamamoto teaches storing programs (i.e., software) in a
program storage area, and therefore teaches information programmed into
firmware as recited in claim 41.
CONCLUSION
(1) The Examiner has not erred in rejecting claims 41--44, 46-54,
56-62, 64--72, and 74--76 as being unpatentable under 35 U.S.C. § 103(a).
(2) Claims 41--44, 46-54, 56-62, 64--72, and 74--76 are not
patentable.
DECISION
The Examiner's rejection of claims 41--44, 46-54, 56-62, 64--72, and
74--76 is affirmed.
8
Appeal2014-005080
Application 11/964,057
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
9